BJT biasing techniques

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WHAT is biasing?

The active region conditions for an npn BJT:

• Base–Emitter junction forward biased ($V_{BE}\approx 0.7\text{ V}$ silicon)
• Base–Collector junction reverse biased ($V_C > V_B$)

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The universal BJT relations (derive these first)

Everything below is built from just three facts:

$I_E = I_C + I_B, \qquad I_C = \beta I_B, \qquad V_{BE}\approx 0.7\text{ V}$

From these: $I_E = I_C + I_B = \beta I_B + I_B = (\beta+1)I_B$ $\alpha = \frac{I_C}{I_E} = \frac{\beta}{\beta+1}$

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Technique 1 — Fixed (Base) Bias

HOW: one resistor $R_B$ from $V_{CC}$ to the base, $R_C$ in the collector.

Apply KVL to the base loop:

\;\;\Rightarrow\;\; \boxed{I_B = \frac{V_{CC}-V_{BE}}{R_B}}$$ Why this step? The base current is set purely by the fixed supply and $R_B$ — nothing pushes back. Then: $$I_C = \beta I_B = \frac{\beta(V_{CC}-V_{BE})}{R_B}$$ KVL on the **collector loop**: $$V_{CE} = V_{CC} - I_C R_C$$ > [!mistake] "Fixed base bias is stable because $I_B$ is fixed." > Feels right: $I_B$ *is* constant. **But** $I_C=\beta I_B$ — so $I_C$ scales **directly with $\beta$**. Double $\beta$ (heat, or a different chip) and $I_C$ doubles, driving the transistor toward saturation. > **Fix:** use feedback or an emitter resistor so $I_C$ is set by resistors, not $\beta$. **Stability factor** $S=\dfrac{\partial I_C}{\partial I_{CO}}$: for fixed bias $S=\beta+1$ — **worst possible**. --- ## Technique 2 — Collector-to-Base (Feedback) Bias **HOW:** $R_B$ connects from the **collector** (not $V_{CC}$) to the base. KVL base loop (note current through $R_C$ is $I_C+I_B$): $$V_{CC} = (I_C+I_B)R_C + I_B R_B + V_{BE}$$ Solve for $I_B$, use $I_C=\beta I_B$: $$I_B = \frac{V_{CC}-V_{BE}}{R_B + (\beta+1)R_C}$$ $$\boxed{I_C = \frac{\beta(V_{CC}-V_{BE})}{R_B+(\beta+1)R_C}}$$ > [!intuition] Why it self-corrects (negative feedback) > If $I_C$ tries to rise → drop across $R_C$ rises → collector voltage falls → base voltage (fed from collector) falls → $I_B$ falls → $I_C$ pulled back down. The circuit *fights* its own drift. Better than fixed bias, but the AC feedback also reduces gain. --- ## Technique 3 — Voltage-Divider Bias (the workhorse) **HOW:** $R_1,R_2$ form a divider setting the base voltage; $R_E$ in the emitter provides feedback. **Thévenin the base network:** $$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2}, \qquad R_{TH}=R_1\parallel R_2 = \frac{R_1R_2}{R_1+R_2}$$ Why? Replace the divider with one source + one resistance so we can write one clean base loop. KVL base loop: $$V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E$$ Substitute $I_E=(\beta+1)I_B$: $$I_B = \frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E}$$ $$\boxed{I_C \approx I_E = \frac{V_{TH}-V_{BE}}{R_E + \dfrac{R_{TH}}{\beta+1}}}$$ > [!intuition] The magic approximation > Design so that $R_{TH} \ll (\beta+1)R_E$. Then $\dfrac{R_{TH}}{\beta+1}\to 0$ and: > $$I_E \approx \frac{V_{TH}-V_{BE}}{R_E}$$ > **$\beta$ has vanished!** $I_C$ is now set by *resistor values and the supply* — rock-stable across chips and temperature. This is why voltage-divider bias dominates real designs. **Rule of thumb:** make the divider current $\gtrsim 10\,I_B$, i.e. $R_2 \le 0.1\,\beta R_E$. Collector loop: $$V_{CE} = V_{CC} - I_C(R_C+R_E)$$ > [!mistake] Forgetting $R_E$ in the collector loop > Students write $V_{CE}=V_{CC}-I_CR_C$. **Wrong** here — the emitter current also drops voltage across $R_E$. Since $I_C\approx I_E$, the DC load line uses $R_C+R_E$. --- ## Technique 4 — Emitter Bias (dual supply $\pm V$) With $+V_{CC}$ and $-V_{EE}$, base grounded through $R_B$: $$I_E = \frac{V_{EE}-V_{BE}}{R_E + R_B/(\beta+1)} \approx \frac{V_{EE}-V_{BE}}{R_E}$$ Same idea: emitter resistor + a defined reference makes $I_C$ nearly $\beta$-independent. --- ## Worked Examples > [!example] Fixed bias numbers > $V_{CC}=12\text{ V}$, $R_B=470\text{ k}\Omega$, $R_C=2.2\text{ k}\Omega$, $\beta=100$. > **Step 1** $I_B=\dfrac{12-0.7}{470\text{k}}=24.0\ \mu\text{A}$ — *Why?* base loop KVL. > **Step 2** $I_C=100\times24.0\mu=2.40\text{ mA}$ — *Why?* $I_C=\beta I_B$. > **Step 3** $V_{CE}=12-2.40\text{m}\times2.2\text{k}=6.72\text{ V}$ — nice mid-swing. > **Now $\beta\to 200$:** $I_C=4.81\text{ mA}$, $V_{CE}=12-10.6=1.4\text{ V}$ — nearly saturated! **Q-point moved massively** → proof of instability. > [!example] Voltage-divider bias numbers > $V_{CC}=12\text{ V}$, $R_1=47\text{k}$, $R_2=10\text{k}$, $R_E=1\text{k}$, $R_C=2.2\text{k}$, $\beta=100$. > **Step 1** $V_{TH}=12\cdot\frac{10}{57}=2.11\text{ V}$ — *Why?* divider ratio. > **Step 2** $R_{TH}=47\text{k}\parallel10\text{k}=8.25\text{k}$ — *Why?* Thévenin resistance. > **Step 3** $I_E=\dfrac{2.11-0.7}{1\text{k}+8.25\text{k}/101}=\dfrac{1.41}{1082}=1.30\text{ mA}$ — *Why?* base loop with $(\beta+1)$ transform. > **Step 4** $V_{CE}=12-1.30\text{m}(2.2\text{k}+1\text{k})=12-4.16=7.84\text{ V}$. > **Now $\beta\to 200$:** $I_E=\dfrac{1.41}{1000+41.3}=1.35\text{ mA}$ — barely changed (+3.8%)! **This is the whole point.** --- ## Stability factor (why we quantify it) $$S = \frac{\partial I_C}{\partial I_{CO}} = \frac{\beta+1}{1-\beta\frac{\partial I_B}{\partial I_C}}$$ | Scheme | Stability factor $S$ | Verdict | |---|---|---| | Fixed bias | $\beta+1$ | worst | | Collector feedback | $\dfrac{\beta+1}{1+\beta R_C/(R_B+R_C)}$ | better | | Voltage divider | $\dfrac{(\beta+1)(R_{TH}+R_E)}{R_{TH}+(\beta+1)R_E}\to 1$ | best | Smaller $S$ (closer to 1) = more stable. --- > [!recall]- Feynman: explain to a 12-year-old > A transistor is like a water tap that a tiny finger (base current) can turn. But the tap is moody — on a hot day the same finger pushes *way* more water. "Fixed bias" trusts the finger completely, so on hot days you get a flood. "Voltage-divider bias" instead puts a **spring on the tap** (the emitter resistor $R_E$): if too much water flows, the spring pushes back and closes the tap a bit. So no matter how moody the tap, the flow stays steady. That's why real circuits use the spring version. > [!mnemonic] Ordering by stability > **"FoolsCeaselessly Vex Engineers"** → **F**ixed → **C**ollector-feedback → **V**oltage-divider → **E**mitter (dual supply): left = worst, right = best. > For divider design: **"Ten to one"** — divider current ≥ 10× base current. --- ## Active-Recall Flashcards #flashcards/hardware For linear amplification, a BJT must be biased in which region? ::: The active region (BE forward, BC reverse biased). Define the Q-point. ::: The DC quiescent operating point $(I_{CQ}, V_{CEQ})$ set by the bias network. Fixed-bias $I_B$ formula? ::: $I_B=(V_{CC}-V_{BE})/R_B$. Why is fixed bias unstable? ::: $I_C=\beta I_B$ depends directly on $\beta$, which varies with device and temperature. Voltage-divider bias approximate $I_E$? ::: $I_E\approx(V_{TH}-V_{BE})/R_E$, independent of $\beta$. Thévenin equivalents for the divider? ::: $V_{TH}=V_{CC}R_2/(R_1+R_2)$, $R_{TH}=R_1\parallel R_2$. Condition for the $\beta$-independent approximation? ::: $R_{TH}\ll(\beta+1)R_E$ (make divider current ≥ 10×$I_B$). Collector loop for divider bias? ::: $V_{CE}=V_{CC}-I_C(R_C+R_E)$ (both resistors, since $I_C\approx I_E$). How does $R_E$ stabilize the Q-point? ::: Negative feedback: rising $I_C$ raises $I_ER_E$, lowering $V_{BE}$, reducing $I_B$ and $I_C$. Stability factor of fixed bias? ::: $S=\beta+1$ (worst; best is $S\to 1$). Collector-feedback $I_C$ formula? ::: $I_C=\beta(V_{CC}-V_{BE})/[R_B+(\beta+1)R_C]$. Relation between $\alpha$ and $\beta$? ::: $\alpha=\beta/(\beta+1)$. --- ## Connections - [[BJT operating regions]] — active vs cutoff vs saturation - [[DC load line and Q-point]] — where biasing places you on the line - [[Thevenin's theorem]] — used to collapse the voltage divider - [[Small-signal amplifier analysis]] — needs a stable Q-point to work - [[Temperature effects in semiconductors]] — why $\beta$ and $V_{BE}$ drift - [[FET biasing techniques]] — analogous problem for MOSFETs/JFETs - [[Negative feedback]] — the principle behind $R_E$ and collector feedback ## 🖼️ Concept Map ```mermaid flowchart TD BIAS[Biasing sets DC Q-point] QP[Q-point IcQ VceQ] ACT[Active region] MID[Mid load-line swing] REL[Core relations Ie=Ic+Ib Ic=beta*Ib] BETA[Beta unreliable and temp-dependent] GOAL[Make Ic independent of beta] FB[Fixed base bias] CFB[Collector-to-base feedback bias] STAB[Stability factor S] BIAS -->|establishes| QP QP -->|must lie in| ACT ACT -->|centred for| MID REL -->|derive| FB REL -->|derive| CFB BETA -->|motivates| GOAL FB -->|Ic scales with| BETA FB -->|gives S=beta+1 worst| STAB CFB -->|feedback reduces| BETA GOAL -->|achieved by| CFB STAB -->|measures drift of| QP ``` ## 🔊 Hinglish (regional understanding) > [!intuition]- Hinglish mein samjho > Dekho, transistor ko amplifier ki tarah use karna hai to usko "active region" me baithana padta hai — matlab BE junction forward bias aur BC junction reverse bias. Is DC setup ko hi **biasing** bolte hain, aur jis point pe transistor rest karta hai usko **Q-point** ($I_{CQ}, V_{CEQ}$) kehte hain. Q-point ko load line ke beech me rakhna best hota hai taaki signal upar-neeche dono taraf clip na ho. > > Sabse bada dushman hai **$\beta$** — ye har chip me alag hota hai aur garmi me badh jaata hai. **Fixed bias** me $I_B=(V_{CC}-V_{BE})/R_B$ fix hota hai, par $I_C=\beta I_B$ hone ki wajah se agar $\beta$ double ho gaya to $I_C$ bhi double — transistor saturation me chala jaata hai ![[audio/2.4.06-BJT-biasing-techniques.mp3]]