BJT biasing techniques — Hinglish notes

2.4.6 · Hardware › Transistors: BJT & FET

Biasing KYA hai?

Ek npn BJT ke liye active region conditions:

Base–Emitter junction forward biased ( $V_{B E} \approx 0.7 V$ silicon)
Base–Collector junction reverse biased ( $V_{C} > V_{B}$ )

Universal BJT relations (pehle inhe derive karo)

Neeche sab kuch sirf teen baaton se bana hai:

$I_{E} = I_{C} + I_{B}, I_{C} = β I_{B}, V_{B E} \approx 0.7 V$

Inse: $I_{E} = I_{C} + I_{B} = β I_{B} + I_{B} = (β + 1) I_{B}$ $α = \frac{I _{C}}{I _{E}} = \frac{β}{β + 1}$

Technique 1 — Fixed (Base) Bias

TARIKA: ek resistor $R_{B}$ $V_{C C}$ se base tak, $R_{C}$ collector mein.

Base loop par KVL lagao:

\;\;\Rightarrow\;\; \boxed{I_B = \frac{V_{CC}-V_{BE}}{R_B}}$$ Yeh step kyun? Base current poori tarah fixed supply aur $R_B$ se set hoti hai — kuch pushback nahi karta. Phir: $$I_C = \beta I_B = \frac{\beta(V_{CC}-V_{BE})}{R_B}$$ **Collector loop** par KVL: $$V_{CE} = V_{CC} - I_C R_C$$ > [!mistake] "Fixed base bias stable hai kyunki $I_B$ fixed hai." > Sahi lagta hai: $I_B$ *constant* hai. **Lekin** $I_C=\beta I_B$ — toh $I_C$ seedha $\beta$ ke saath scale karta hai. $\beta$ double karo (garmi, ya alag chip) aur $I_C$ double ho jaata hai, transistor ko saturation ki taraf le jaata hai. > **Fix:** feedback ya emitter resistor use karo taaki $I_C$ resistors se set ho, $\beta$ se nahi. **Stability factor** $S=\dfrac{\partial I_C}{\partial I_{CO}}$: fixed bias ke liye $S=\beta+1$ — **sabse kharaab**. --- ## Technique 2 — Collector-to-Base (Feedback) Bias **TARIKA:** $R_B$ **collector** se ($V_{CC}$ se nahi) base tak connect hota hai. Base loop KVL (dhyan do $R_C$ mein current $I_C+I_B$ hai): $$V_{CC} = (I_C+I_B)R_C + I_B R_B + V_{BE}$$ $I_B$ ke liye solve karo, $I_C=\beta I_B$ use karo: $$I_B = \frac{V_{CC}-V_{BE}}{R_B + (\beta+1)R_C}$$ $$\boxed{I_C = \frac{\beta(V_{CC}-V_{BE})}{R_B+(\beta+1)R_C}}$$ > [!intuition] Yeh self-correct kyun karta hai (negative feedback) > Agar $I_C$ badhne ki koshish kare → $R_C$ par drop badhe → collector voltage gire → base voltage (collector se fed) gire → $I_B$ gire → $I_C$ neeche aa jaaye. Circuit apne aap apna drift *rokta* hai. Fixed bias se behtar, lekin AC feedback gain bhi kam kar deta hai. --- ## Technique 3 — Voltage-Divider Bias (the workhorse) **TARIKA:** $R_1,R_2$ ek divider banate hain jo base voltage set karta hai; emitter mein $R_E$ feedback deta hai. **Base network ka Thévenin nikalo:** $$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2}, \qquad R_{TH}=R_1\parallel R_2 = \frac{R_1R_2}{R_1+R_2}$$ Kyun? Divider ko ek source + ek resistance se replace karo taaki ek clean base loop likh sakein. Base loop KVL: $$V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E$$ $I_E=(\beta+1)I_B$ substitute karo: $$I_B = \frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E}$$ $$\boxed{I_C \approx I_E = \frac{V_{TH}-V_{BE}}{R_E + \dfrac{R_{TH}}{\beta+1}}}$$ > [!intuition] Magical approximation > Design aise karo ki $R_{TH} \ll (\beta+1)R_E$. Tab $\dfrac{R_{TH}}{\beta+1}\to 0$ aur: > $$I_E \approx \frac{V_{TH}-V_{BE}}{R_E}$$ > **$\beta$ gayab ho gaya!** $I_C$ ab *resistor values aur supply* se set hota hai — chips aur temperature ke paas rock-stable. Issi liye voltage-divider bias real designs mein dominant hai. **Rule of thumb:** divider current $\gtrsim 10\,I_B$ banao, yaani $R_2 \le 0.1\,\beta R_E$. Collector loop: $$V_{CE} = V_{CC} - I_C(R_C+R_E)$$ > [!mistake] Collector loop mein $R_E$ bhool jaana > Students likhte hain $V_{CE}=V_{CC}-I_CR_C$. Yahan **galat** hai — emitter current $R_E$ par bhi voltage drop karta hai. Kyunki $I_C\approx I_E$, DC load line $R_C+R_E$ use karta hai. --- ## Technique 4 — Emitter Bias (dual supply $\pm V$) $+V_{CC}$ aur $-V_{EE}$ ke saath, base $R_B$ ke through ground se connected: $$I_E = \frac{V_{EE}-V_{BE}}{R_E + R_B/(\beta+1)} \approx \frac{V_{EE}-V_{BE}}{R_E}$$ Same idea: emitter resistor + ek defined reference $I_C$ ko almost $\beta$-independent banata hai. --- ## Worked Examples > [!example] Fixed bias ke numbers > $V_{CC}=12\text{ V}$, $R_B=470\text{ k}\Omega$, $R_C=2.2\text{ k}\Omega$, $\beta=100$. > **Step 1** $I_B=\dfrac{12-0.7}{470\text{k}}=24.0\ \mu\text{A}$ — *Kyun?* base loop KVL. > **Step 2** $I_C=100\times24.0\mu=2.40\text{ mA}$ — *Kyun?* $I_C=\beta I_B$. > **Step 3** $V_{CE}=12-2.40\text{m}\times2.2\text{k}=6.72\text{ V}$ — achha mid-swing. > **Ab $\beta\to 200$:** $I_C=4.81\text{ mA}$, $V_{CE}=12-10.6=1.4\text{ V}$ — almost saturated! **Q-point bahut zyada shift ho gaya** → instability ka proof. > [!example] Voltage-divider bias ke numbers > $V_{CC}=12\text{ V}$, $R_1=47\text{k}$, $R_2=10\text{k}$, $R_E=1\text{k}$, $R_C=2.2\text{k}$, $\beta=100$. > **Step 1** $V_{TH}=12\cdot\frac{10}{57}=2.11\text{ V}$ — *Kyun?* divider ratio. > **Step 2** $R_{TH}=47\text{k}\parallel10\text{k}=8.25\text{k}$ — *Kyun?* Thévenin resistance. > **Step 3** $I_E=\dfrac{2.11-0.7}{1\text{k}+8.25\text{k}/101}=\dfrac{1.41}{1082}=1.30\text{ mA}$ — *Kyun?* $(\beta+1)$ transform ke saath base loop. > **Step 4** $V_{CE}=12-1.30\text{m}(2.2\text{k}+1\text{k})=12-4.16=7.84\text{ V}$. > **Ab $\beta\to 200$:** $I_E=\dfrac{1.41}{1000+41.3}=1.35\text{ mA}$ — almost nahi badla (+3.8%)! **Yahi toh poora point hai.** --- ## Stability factor (hum ise quantify kyun karte hain) $$S = \frac{\partial I_C}{\partial I_{CO}} = \frac{\beta+1}{1-\beta\frac{\partial I_B}{\partial I_C}}$$ | Scheme | Stability factor $S$ | Verdict | |---|---|---| | Fixed bias | $\beta+1$ | sabse kharaab | | Collector feedback | $\dfrac{\beta+1}{1+\beta R_C/(R_B+R_C)}$ | behtar | | Voltage divider | $\dfrac{(\beta+1)(R_{TH}+R_E)}{R_{TH}+(\beta+1)R_E}\to 1$ | sabse achha | Chhota $S$ (1 ke kareeb) = zyada stable. --- > [!recall]- Feynman: ek 12-saal ke bachche ko samjhao > Transistor ek paani ka naal (tap) jaisa hai jise ek choti ungli (base current) khol aur band kar sakti hai. Lekin naal mood-yy hai — garmi ke din mein usi ungli se *bahut zyada* paani aata hai. "Fixed bias" ungli par poora bharosa karta hai, isliye garmi ke din mein baadhh aa jaati hai. "Voltage-divider bias" naal par ek **spring** lagata hai (emitter resistor $R_E$): agar zyada paani behe, spring pushback karta hai aur naal thoda band kar deta hai. Toh naal kitna bhi mood-yy ho, flow stable rehta hai. Issi liye real circuits mein spring wala version use hota hai. > [!mnemonic] Stability ka order > **"FoolsCeaselessly Vex Engineers"** → **F**ixed → **C**ollector-feedback → **V**oltage-divider → **E**mitter (dual supply): left = sabse kharaab, right = sabse achha. > Divider design ke liye: **"Ten to one"** — divider current ≥ 10× base current. --- ## Active-Recall Flashcards #flashcards/hardware Linear amplification ke liye BJT ko kis region mein bias karna chahiye? ::: Active region mein (BE forward, BC reverse biased). Q-point define karo. ::: DC quiescent operating point $(I_{CQ}, V_{CEQ})$ jo bias network set karta hai. Fixed-bias $I_B$ formula? ::: $I_B=(V_{CC}-V_{BE})/R_B$. Fixed bias unstable kyun hai? ::: $I_C=\beta I_B$ seedha $\beta$ par depend karta hai, jo device aur temperature ke saath vary karta hai. Voltage-divider bias ka approximate $I_E$? ::: $I_E\approx(V_{TH}-V_{BE})/R_E$, $\beta$ se independent. Divider ke Thévenin equivalents? ::: $V_{TH}=V_{CC}R_2/(R_1+R_2)$, $R_{TH}=R_1\parallel R_2$. $\beta$-independent approximation ke liye condition? ::: $R_{TH}\ll(\beta+1)R_E$ (divider current ≥ 10×$I_B$ banao). Divider bias ke liye collector loop? ::: $V_{CE}=V_{CC}-I_C(R_C+R_E)$ (dono resistors, kyunki $I_C\approx I_E$). $R_E$ Q-point ko stabilize kyun karta hai? ::: Negative feedback: badhta $I_C$, $I_ER_E$ badhata hai, $V_{BE}$ girata hai, $I_B$ aur $I_C$ kam ho jaate hain. Fixed bias ka stability factor? ::: $S=\beta+1$ (sabse kharaab; sabse achha $S\to 1$ hai). Collector-feedback $I_C$ formula? ::: $I_C=\beta(V_{CC}-V_{BE})/[R_B+(\beta+1)R_C]$. $\alpha$ aur $\beta$ mein relation? ::: $\alpha=\beta/(\beta+1)$. --- ## Connections - [[BJT operating regions]] — active vs cutoff vs saturation - [[DC load line and Q-point]] — biasing load line par kahan place karta hai - [[Thevenin's theorem]] — voltage divider collapse karne ke liye use hota hai - [[Small-signal amplifier analysis]] — stable Q-point chahiye kaam karne ke liye - [[Temperature effects in semiconductors]] — $\beta$ aur $V_{BE}$ kyun drift karte hain - [[FET biasing techniques]] — MOSFETs/JFETs ke liye analogous problem - [[Negative feedback]] — $R_E$ aur collector feedback ke peeche ka principle ## 🖼️ Concept Map ```mermaid flowchart TD BIAS[Biasing sets DC Q-point] QP[Q-point IcQ VceQ] ACT[Active region] MID[Mid load-line swing] REL[Core relations Ie=Ic+Ib Ic=beta*Ib] BETA[Beta unreliable and temp-dependent] GOAL[Make Ic independent of beta] FB[Fixed base bias] CFB[Collector-to-base feedback bias] STAB[Stability factor S] BIAS -->|establishes| QP QP -->|must lie in| ACT ACT -->|centred for| MID REL -->|derive| FB REL -->|derive| CFB BETA -->|motivates| GOAL FB -->|Ic scales with| BETA FB -->|gives S=beta+1 worst| STAB CFB -->|feedback reduces| BETA GOAL -->|achieved by| CFB STAB -->|measures drift of| QP ```