A store S enters the FIFO store buffer and retires from the pipeline; it drains to memory later. → the core proceeds.
A subsequent load L checks the buffer (store-forwarding) then goes to cache. It can complete while S is still buffered. → L finishes before S is globally visible ⇒ S→L reordered. ✅ explains the SB outcome.
Stores are a FIFO buffer ⇒ they drain in program order ⇒ S→S preserved.
Loads are not buffered this way and are ordered relative to each other and to earlier stores in the buffer ⇒ L→L, L→S preserved.
That's the whole TSO rulebook, derived — no memorization needed.
Imagine four friends passing notes in class. Each friend writes their notes in order, but the notes travel around the room at different speeds. So Anna might get Bob's second note before his first! A memory consistency model is the class rule that says how out-of-order the notes are allowed to arrive. A strict rule says everyone must read all notes in the exact same order (slow but simple). A relaxed rule lets notes fly around fast, but if you really need someone to see two of your notes in order, you shout "FENCE!" and wait until the first note is delivered before sending the second.
A contract specifying which global orderings of loads/stores across processors are legal — defines allowed outcomes of a shared-memory program.
Consistency vs coherence?
Coherence orders writes to a single address; consistency orders operations across different addresses.
Statement of Sequential Consistency (SC)?
Result equals some single total interleaving of all ops in which each processor's ops appear in program order.
Which single reordering does TSO allow, and why?
Store→Load, because a store sits in a FIFO store buffer while a later load bypasses it via cache/store-forwarding.
Can r10 && r20 in the Store-Buffering test under SC?
No — it requires an ordering cycle. Under TSO/x86: Yes (store buffers).
What does a memory fence do?
Forces all memory ops before it to become globally visible before any op after it; e.g. MFENCE drains the store buffer.
Why doesn't C volatile give thread ordering?
It stops compiler register-caching but emits no hardware fences; use std::atomic with acquire/release/seq_cst.
What is IRIW and what distinguishes weak models on it?
Independent Reads of Independent Writes; multi-copy-atomic models (SC/TSO) forbid two cores seeing two writes in different orders, non-multi-copy (POWER/ARM) allow it.
General test for whether an outcome is legal under SC?
Build the required ordering edges; if they form a cycle, the outcome is illegal.
Dekho, jab ek hi memory ko multiple cores ek saath read/write karte hain, tab hardware speed ke liye operations ko reorder, buffer aur delay karta hai. Har core apne aap mein toh sahi chalta hai, lekin doosre cores ko memory operations alag order mein dikh sakte hain. Memory consistency model ek contract hai jo batata hai ki kaun-kaun se orderings allowed hain. Iske bina "yeh load kaunsi value return karega?" ka koi pakka jawab hi nahi hota.
Sabse strong model hai Sequential Consistency (SC) — socho ek single global switch hai jo baari-baari cores ke ops chalata hai, par kisi core ka apna program order kabhi todta nahi. Simple hai par slow. TSO (x86) thoda relaxed hai: ek store apne store buffer mein baith jaata hai aur core aage badh jaata hai, isliye baad ka load usse bypass kar sakta hai (sirf S→L reorder allowed). ARM/POWER toh bahut weak hain — almost sab kuch reorder ho sakta hai.
Yaad rakhne ka tareeka: TSO ka "one sin" — Stores Look Late (S→L). Jab tumhe cross-core ordering chahiye hi chahiye (lock, flag pattern), tab tum fence/barrier lagate ho jo store buffer ko drain kar deta hai aur ordering wapas la deta hai. Yeh 80/20 rule hai — sirf synchronization points par fence lagao, baaki 80% code fast chalne do.
Important trap: C ka volatile thread ordering nahi deta — woh sirf compiler ko register mein cache karne se rokta hai. Real ordering ke liye std::atomic (acquire/release/seq_cst) use karo. Aur yeh mat socho ki "x86 pe chal gaya matlab sab jagah chalega" — mobile ka ARM weak hai, wahan missing fence bug de dega.
