Memory consistency models

5.4.16 · Hardware › Memory Hierarchy & Caches

WHAT hai ek memory consistency model?

Do cheezein jo yeh NAHI hai, taaki hum confuse na hon:

WHY hamen ek ki zaroorat hai?

Canonical litmus test (Dekker / Store Buffering)

Initial: x = 0, y = 0.

Core 1	Core 2
`x = 1` (S1)	`y = 1` (S3)
`r1 = y` (L2)	`r2 = x` (L4)

Sawaal (Forecast-then-Verify — padhne se pehle predict karo!): Kya r1 == 0 && r2 == 0 ho sakta hai?

Ek strong model ke under (Sequential Consistency): Nahi. Koi na koi store globally pehle hoga.
Ek weak model ke under (TSO / x86 with store buffers): Haan — dono stores store buffers mein baithe hain, dono loads memory se stale 0 padhte hain.

Strong se weak tak ka spectrum

HOW formally reason karte hain? "Reorderings allowed" table

Har model ko aise samjho: do same-core memory ops ke beech char orderings mein se kaun si woh enforce karta hai?

Model	L→L	L→S	S→S	S→L	Notes
SC	✅	✅	✅	✅	sabhi preserved
TSO	✅	✅	✅	❌	store buffer bypass
PSO	✅	✅	❌	❌	+ relaxed S→S
Weak/ARM	❌	❌	❌	❌	fences chahiye

(✅ = ordering enforce hoti hai; ❌ = reorder ho sakti hai.)

TSO sirf S→L kyun allow karta hai — first principles se derive karna

Ek store $S$ FIFO store buffer mein jaata hai aur pipeline se retire hota hai; baad mein memory mein drain hota hai. → core aage badhta hai.
Ek baad ka load $L$ buffer check karta hai (store-forwarding) phir cache jaata hai. Yeh complete ho sakta hai jabki $S$ abhi bhi buffered hai. → $L$ finish hota hai $S$ ke globally visible hone se pehle ⇒ S→L reordered. ✅ SB outcome explain hota hai.
Stores ek FIFO buffer hain ⇒ woh program order mein drain hote hain ⇒ S→S preserved.
Loads is tarah buffered nahi hote aur dono ek doosre ke relative aur buffer mein pehle stores ke relative ordered hote hain ⇒ L→L, L→S preserved.

Yeh pura TSO rulebook hai, derive kiya gaya — koi memorization nahi chahiye.

Worked examples

Worked example Example 1 — Message passing (flag pattern)

Init data = 0, flag = 0.

Core 1 (producer)	Core 2 (consumer)
`data = 42` (S1)	`while(flag==0){}` (L3)
`flag = 1` (S2)	`r = data` (L4)

Q: ARM (weak) par, kya r 0 ho sakta hai even after hum ne flag==1 dekha? A: Haan.

Yeh step kyun? Weak hardware par S1 aur S2 ka koi S→S ordering nahi hoti — flag=1, data=42 se pehle visible ho sakta hai. Consumer flag dekhta hai, stale data padhta hai.
Fix: producer ko S1 aur S2 ke beech ek release fence chahiye; consumer ko L3 ke baad ek acquire fence chahiye. TSO/x86 par S→S preserved hai, toh yeh pattern fence ke bina kaam karta hai.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Sochiye chaar doost class mein notes pass kar rahe hain. Har doost apne notes order mein likhta hai, lekin notes room mein alag-alag speeds se travel karte hain. Toh Anna ko Bob ka doosra note uske pehle waale se pehle mil sakta hai! Ek memory consistency model woh class rule hai jo kehta hai notes kitne out-of-order aa sakte hain. Ek strict rule kehta hai sab ko sabhi notes exact same order mein padhne chahiye (slow hai par simple). Ek relaxed rule notes ko fast fly karne deta hai, lekin agar aap sach mein chahte ho ki koi aapke do notes order mein dekhe, toh aap "FENCE!" chillaate ho aur wait karte ho jab tak pehla note deliver nahi ho jaata phir doosra bhejte ho.

Common mistakes

Flashcards

Memory consistency model kya hai?

Ek contract jo specify karta hai ki processors ke across loads/stores ke kaun se global orderings legal hain — shared-memory program ke allowed outcomes define karta hai.

Consistency vs coherence?

Coherence ek address par writes order karta hai; consistency alag-alag addresses ke across operations order karta hai.

Sequential Consistency (SC) ka statement?

Result kisi ek single total interleaving ke barabar hota hai sabhi ops ka jismein har processor ke ops program order mein dikhte hain.

TSO kaun si ek reordering allow karta hai, aur kyun?

Store→Load, kyunki ek store FIFO store buffer mein baith jaata hai jabki baad ka load cache/store-forwarding ke zariye ise bypass kar leta hai.

SC ke under Store-Buffering test mein r10 && r20 ho sakta hai?

Nahi — iske liye ek ordering cycle chahiye. TSO/x86 ke under: Haan (store buffers).

Memory fence kya karta hai?

Sabhi memory ops jo iske pehle hain unhe force karta hai ki woh iske baad ki kisi bhi op se pehle globally visible ho jayein; e.g. MFENCE store buffer drain karta hai.

C volatile thread ordering kyun nahi deta?

Yeh compiler register-caching rok deta hai lekin koi hardware fences emit nahi karta; std::atomic use karo acquire/release/seq_cst ke saath.

IRIW kya hai aur weak models ko isme kya alag banata hai?

Independent Reads of Independent Writes; multi-copy-atomic models (SC/TSO) forbid karte hain ki do cores do writes alag-alag orders mein dekhein, non-multi-copy (POWER/ARM) allow karte hain.

SC ke under outcome legal hai ya nahi ka general test?

Required ordering edges banao; agar woh cycle form karein, toh outcome illegal hai.

Connections

Cache Coherence — per-address sibling; consistency is par build hoti hai.
Store Buffers and Write Buffering — S→L relaxation ka hardware cause.
Memory Barriers and Fences — ordering recover karne ka tool.
Atomic Operations and Locks — fences + consistency guarantees use karke banaye jaate hain.
Out-of-Order Execution — visible reordering ka ek aur source.
C++ Memory Model (acquire-release) — in ideas ka language-level mapping.