This page assumes nothing. Before you touch the parent topic we build every word, symbol, and picture it leans on, one brick at a time. If you have seen none of the notation, start at line one and keep going.
Everything in this topic is a story about these four things, so we draw them first.
Why the topic needs these: every rule we will state is a rule about which loads and stores, done by which cores, can be seen in which order. If you can picture cores as people and memory boxes as pigeonholes on a shared wall, you can picture the entire topic.
We give this a symbol because we will constantly compare it against the order things actually become visible.
Why the topic needs it: the whole question of consistency is "does the order things become visible match program order, or not?" You cannot ask that until you can name program order.
A single core, running alone, always behaves as if it obeyed its own program order. The trouble starts because of one speed trick.
Look at the figure. The store x = 1 is still sitting in Core 1's buffer (not yet on the wall). Meanwhile Core 2 does a load of x and reads the old value 0 from the wall, because the new value never got there yet.
Why the topic needs it: the parent note's headline litmus test (both cores read stale 0) is literally a picture of two store buffers holding writes back. See Store Buffers and Write Buffering for the deeper version.
We keep saying "visible." Let's pin it down, because it is the hidden hero of the whole subject.
Why the topic needs it: phrases like "S→L reordering" mean "the load became globally visible before the earlier store did." Without the idea of a visibility moment, "reordered" has no meaning.
Every model in the parent is described by one tiny table with four entries. Here is where those four come from.
Take any two memory operations from the same core, in program order. Each is either a Load (L) or a Store (S). Two choices, two slots → exactly four combinations:
✅ means "enforced": the model promises the later op will not overtake the earlier one, as seen by other cores.
❌ means "may be reordered": the hardware is allowed to let the later op become visible first.
Why the topic needs it: the entire strong-to-weak spectrum is just which of these four boxes are ✅. Strong models (Sequential Consistency) tick all four; TSO ticks three and lets only S→L slip; weak models (ARM/POWER) tick none by default. That's the whole map. This connects to Out-of-Order Execution, which is the engine that does the reordering.
The parent proves things by "finding a cycle." Here is what that means with zero prior knowledge.
Why the topic needs it: Example 2 in the parent (r1==0 && r2==0 forbidden under Sequential Consistency) is only the sentence "these constraints form a cycle." Once you can draw the graph, you can settle any test yourself.
You will meet two rescue tools. We name them now; deeper mechanics live in their own notes.
Why the topic needs it: on weak hardware the model gives you almost no free ordering, so you earn back the ordering you need with fences and atomics. The high-level programmer version of these is the C++ Memory Model (acquire-release). And note: consistency (ordering across addresses) sits on top of Cache Coherence (agreement about one address) — the parent stresses these are different.
Read top to bottom: nouns (cores, loads, stores) feed program order; the store buffer plus the idea of a visibility moment produce reordering; reordering across the four pairs is scored by the cycle test; that scoring is the consistency model, with fences and coherence bolted on.
Cover the right side and answer out loud. If any answer is shaky, reread that section before the parent.
What is the difference between a register and a shared memory box?
A register is private to one core and invisible to others; a shared box (like x) is the value all cores can load and store.
What does r1 = y mean in words?
Load: read the current value out of shared box y and copy it into this core's private register r1.
What does apob say?
In this core's source code, operation a was written before operation b (program order).
Why can a load finish before an earlier store on the same core?
The store waits in the FIFO store buffer while the core races ahead; the load isn't held in that line, so it completes before the store drains to memory.
What does "globally visible" mean for a store?
Its value has reached shared memory, so any other core loading that box would now see the new value.
Name the four program-order pairs.
L→L, L→S, S→S, S→L.
In the ordering-model table, what do ✅ and ❌ mean?
✅ = that pair's order is enforced (guaranteed to other cores); ❌ = the hardware may let the later op become visible first.
Why does a cycle in the ordering graph prove an outcome is impossible?
A cycle means an operation must happen before itself, which is contradictory, so that outcome is illegal.
What does a fence do to the four pairs?
At its location it forces earlier ops to become globally visible before later ones — flipping a ❌ back to ✅ there.
How is consistency different from coherence?
Coherence is agreement about the order of writes to a single address; consistency is the rulebook for ordering ops across different addresses.
