Question bank — Memory consistency models

True. In the table TSO's S→S is ✅, and the mechanism is the FIFO store buffer: stores drain in the order issued, so every observer sees them in that one order. See Store Buffers and Write Buffering.

True. Via store-forwarding, a later load reads the buffered value directly from the store buffer, so the core sees its own write immediately even though other cores don't yet — this is exactly the S→L (❌) relaxation in action.

False. SC fixes the ordering (a single total interleaving respecting each core's program order — all four pairs ✅) but is typically the slowest model precisely because ✅ on S→L forbids the store-buffer bypass that gives real speed.

False. Coherence orders writes to one address; consistency (the whole four-pair table) orders ops across different addresses. Coherence is necessary but strictly weaker. See Cache Coherence.

True. The producer does two stores (data=42 then flag=1); TSO's S→S is ✅, so data is visible before flag, and any consumer that sees the flag also sees the data. See Memory Barriers and Fences.

False. A fence only forces ✅ ordering across its own position (ops before it vs ops after it); everywhere else the weak model's ❌ freedoms still apply. It buys back SC locally, not globally.

False in effect. Locks embed the necessary fences, converting the relevant ❌ pairs back to ✅ at the lock boundaries, so a race-free program behaves as if SC — the SC-for-DRF guarantee. See Atomic Operations and Locks.

False. volatile only stops the compiler from caching a value in a register; it emits no hardware fences, so every ❌ in the weak-model row stays ❌ across threads. Use atomics from the C++ Memory Model (acquire-release) instead.

True. Letting a later load complete before an earlier store drains is an S→L reorder (the ❌ cell), and that alone lets both loads read stale 0. See Out-of-Order Execution.

False. SC keeps all four pairs ✅ and enforces a single global order of all ops, so all readers agree on the order of the two independent writes.

Error: TSO preserves L→L (✅ in the table). The only ❌ in TSO's row is S→L (a store bypassed by a later load). Mnemonic: "Stores Look Late."

Error: a fence slows the core — it stalls until the buffer drains. Its purpose is to convert a ❌ pair back to ✅ (correctness); the cost is performance, so you place it only where ordering is needed.

Error: on ARM all four pairs are ❌, so you need both — a release fence on the producer (forces data=42 visible before flag=1) and an acquire fence on the consumer (forces the flag-read before the data read). One side alone leaves the other's reorder open.

Error: coherence only orders writes to the same address. The cross-address "x then y" question is the S→S pair of the consistency table, not coherence.

Error: TSO governs ordering (the four-pair table), not atomicity of a read-modify-write. A LOCK prefix (or MFENCE) is still needed for atomic increments and to force the S→L cell back to ✅. See Atomic Operations and Locks.

Error: even one core can have its store buffered — its own program order stays intact from its viewpoint (store-forwarding), but the global visibility order of that store to other cores is delayed.

Because only stores are buffered. The buffered store lets a later load finish first (S→L → ❌); the FIFO keeps S→S ✅, and non-buffered loads keep L→L and L→S ✅.

Store-forwarding: a later load to the same address reads the pending value straight from the buffer, so the core always sees a consistent, in-order view of its own memory.

Label the ops: S1 = Core 1 writes x=1, L2 = Core 1 reads y; S3 = Core 2 writes y=1, L4 = Core 2 reads x. The bad outcome r1==0 means L2 read y before S3 wrote it, i.e. L2 < S3 in the global order; r2==0 means L4 < S1. Program order adds S1 < L2 and S3 < L4. Chaining gives S1 < L2 < S3 < L4 < S1 — a cycle, which no single total order can contain. Hence SC forbids it.

They keep almost every ❌ open so ordinary memory ops run reordered and fast; the programmer inserts fences only at the handful of synchronization points (locks, flags) that actually need ✅, trading a little effort for large speedups on many-core hardware.

Those models are non-multi-copy-atomic (defined above): a store can reach different cores at different times, so two readers may observe two writes in opposite orders. TSO is multi-copy-atomic with a single total store order, forbidding it.

A fence forces ✅ only for pairs straddling its position (before → after); it says nothing about ops far from it, so unfenced regions keep the weak model's ❌ freedoms.

No. With no other observer, program order is preserved from that core's own view via store-forwarding — every reorder is invisible, so all rows of the table look identical.

Coherence takes over: all cores agree on a single order of writes to that one address, regardless of how weak the consistency model's four-pair row is.

Another core may see them in either order (S→S is ❌ on ARM), including seeing the second store's effect while the first is still not visible.

No. L→S is ✅ on TSO (only S→L is ❌), so the load is globally ordered before the store.

For S→S ordering it's redundant (TSO already has that cell ✅), but it does drain the buffer and force the surrounding S→L cell back to ✅ — so it's not a no-op, just not needed for the S→S guarantee.

SC. Fencing every boundary forces every ❌ back to ✅, recovering a single total order — at maximum performance cost.

The fence still enforces ordering semantically, but has near-zero cost since there is nothing to drain — the stall is proportional to the number of pending stores.