Yeh page kuch bhi assume nahi karta. Parent topic ko touch karne se pehle hum har word, symbol, aur picture ek-ek karke banate hain. Agar tumne yeh notation pehle kabhi nahi dekha, toh line one se shuru karo aur chalte raho.
Is topic mein sab kuch inhi chaar cheezein ki kahani hai, toh pehle inhe draw karte hain.
Topic ko yeh kyun chahiye: jo bhi rule hum batayenge woh ek rule hai which loads aur stores, kis core ne kiye, kinhe kis order mein dikhte hain. Agar tum cores ko log aur memory boxes ko shared wall ke pigeonholes imagine karo, toh poora topic imagine kar sakte ho.
Hum ise ek symbol dete hain kyunki hum ise constantly us order ke against compare karte rahenge jisme cheezein actually visible hoti hain.
Topic ko yeh kyun chahiye: consistency ka poora sawaal yahi hai "kya cheezein visible hone ki order program order se match karti hai, ya nahi?" Yeh pooch nahi sakte jab tak program order ko naam nahi de sakte.
Ek akela core, akele run karta hua, hamesha behave karta hai jaise apna program order follow kar raha ho. Takleef ek speed trick ki wajah se shuru hoti hai.
Figure dekho. Store x = 1 abhi bhi Core 1 ke buffer mein baitha hai (wall tak pahuncha nahi hai). Isi beech Core 2 x ka load karta hai aur wall se purani value 0 padhta hai, kyunki nayi value wahan abhi tak pahunchi hi nahi.
Topic ko yeh kyun chahiye: parent note ka headline litmus test (dono cores stale 0 read karte hain) literally do store buffers ki picture hai jo writes rokke baithte hain. Deeper version ke liye dekho Store Buffers and Write Buffering.
Hum baar-baar "visible" kehte hain. Ise pin down karte hain, kyunki yeh poore subject ka hidden hero hai.
Topic ko yeh kyun chahiye: "S→L reordering" jaise phrases ka matlab hai "load globally visible hua earlier store se pehle." Visibility moment ke idea ke bina, "reordered" ka koi matlab nahi.
Parent mein har model ko chaar entries wale ek chhote table se describe kiya jata hai. Yeh chaar kahan se aate hain, yahan se.
Ek hi core ke koi do memory operations lo, program order mein. Har ek ya toh Load (L) hai ya Store (S). Do choices, do slots → exactly chaar combinations:
✅ matlab "enforced": model promise karta hai ki baad wala op pehle wale ko overtake nahi karega, doosre cores ki nazar mein.
❌ matlab "may be reordered**: hardware allow karta hai ki baad wala op pehle visible ho jaaye.
Topic ko yeh kyun chahiye: poora strong-to-weak spectrum sirf inhi chaar boxes mein se kaun ✅ hain ki baat hai. Strong models (Sequential Consistency) charon tick karte hain; TSO teen tick karta hai aur sirf S→L slip karne deta hai; weak models (ARM/POWER) default par koi bhi tick nahi karte. Yahi poora map hai. Yeh Out-of-Order Execution se connect hota hai, jo reordering karne wala engine hai.
Parent "cycle dhundhne" se cheezein prove karta hai. Bina kisi prior knowledge ke yeh kya matlab rakhta hai, yahan samjhate hain.
Topic ko yeh kyun chahiye: Parent mein Example 2 (r1==0 && r2==0 Sequential Consistency ke under forbidden) sirf yeh sentence hai "yeh constraints ek cycle banate hain." Ek baar graph draw kar sako, toh koi bhi test khud settle kar sakte ho.
Do rescue tools milenge. Inhe abhi naam dete hain; deeper mechanics apne notes mein hain.
Topic ko yeh kyun chahiye: weak hardware par model tumhe almost koi free ordering nahi deta, toh tum fences aur atomics se woh ordering earn back karte ho jis ordering ki zaroorat hai. In cheezein ka high-level programmer version hai C++ Memory Model (acquire-release). Aur note karo: consistency (ordering across addresses) Cache Coherence ke upar baithti hai (ek address ke baare mein agreement) — parent stress karta hai ki yeh alag-alag cheezein hain.
Top to bottom padhna: nouns (cores, loads, stores) program order ko feed karte hain; store buffer aur visibility moment ka idea reordering produce karta hai; chaar pairs mein reordering cycle test se score hoti hai; woh scoring hi consistency model hai, jisme fences aur coherence jude hain.
Right side cover karo aur zor se jawab do. Agar koi jawab shaky hai, parent se pehle us section ko dobara padhna.
Ek register aur shared memory box mein kya fark hai?
Register ek core ka private hota hai aur doosron ko dikhta nahi; ek shared box (jaise x) woh value hai jo saare cores load aur store kar sakte hain.
r1 = y ka matlab words mein kya hai?
Load: shared box y se current value padhna aur ise is core ke private register r1 mein copy karna.
apob kya kehta hai?
Is core ke source code mein, operation a operation b se pehle likha gaya tha (program order).
Ek load usi core ke earlier store se pehle kyun complete ho sakta hai?
Store FIFO store buffer mein wait karta hai jabki core aage bhaag jaata hai; load us line mein nahi rukta, toh woh complete hota hai store ke memory tak drain hone se pehle.
Store ke liye "globally visible" ka matlab kya hai?
Uski value shared memory tak pahunch gayi hai, toh koi bhi doosra core jo woh box load kare ab nayi value dekhega.
Chaar program-order pairs ke naam batao.
L→L, L→S, S→S, S→L.
Ordering-model table mein ✅ aur ❌ ka matlab kya hai?
✅ = us pair ka order enforced hai (doosre cores ko guaranteed); ❌ = hardware baad wale op ko pehle visible hone de sakta hai.
Ordering graph mein cycle kyun prove karta hai ki ek outcome impossible hai?
Ek cycle ka matlab hai ek operation khud se pehle hona chahiye, jo contradictory hai, isliye woh outcome illegal hai.
Fence chaar pairs ke saath kya karta hai?
Apni location par woh earlier ops ko globally visible hone par majboor karta hai baad wale se pehle — ❌ ko wahan ✅ mein flip karta hai.
Consistency aur coherence mein kya fark hai?
Coherence ek single address par writes ke order ke baare mein agreement hai; consistency alag-alag addresses par operations order karne ka rulebook hai.
