Load-use hazard and stalls

What is a Load-Use Hazard?

A load-use data hazard occurs when an instruction immediately following a load instruction depends on the loaded data. Unlike ALU-ALU hazards (which forwarding solves), load hazards require a stall because:

Load completes in MEM stage (end of cycle 4)
Dependent instruction needs data at the START of its EX stage (start of cycle 4 for the very next instruction)
Forwarding can't bridge this gap — the data doesn't exist yet when needed (it only appears at the end of cycle 4)

Why Forwarding Alone Fails for Loads

The Timeline Problem:

Cycle:     1    2    3    4    5
lw  $2, 0($1)   IF   ID   EX   MEM  WB   ← data available END of cycle 4 (MEM)
add $4, $2, $3       IF   ID   EX   MEM  ← needs $2 START of cycle 4 (EX)

Even with forwarding from MEM/WB → EX, the add instruction's EX stage begins at the start of cycle 4, but the load's data is only ready at the end of cycle 4. The data doesn't exist yet when the ALU needs it.

After inserting 1-cycle stall:

Cycle:     1    2    3    4    5    6
lw  $2, 0($1)   IF   ID   EX   MEM  WB
add $4, $2, $3       IF   ID  (stall) EX   MEM   ← add held in ID one extra cycle

Now add executes EX in cycle 5. The load's data (available end of cycle 4, held in MEM/WB) is forwarded from MEM/WB → EX at cycle 5. Perfect.

Formula Stall Condition Detection

Insert stall when ** three** conditions hold:

\begin{align} &\text{1. ID/EX.MemRead} = 1 \quad(\text{load instruction in EX stage}) \\ &\text{2. ID/EX.RegisterRt} = \text{IF/ID.RegisterRs} \quad \text{OR} \\ &\quad \text{ID/EX.RegisterRt} = \text{IF/ID.RegisterRt} \quad (\text{register match}) \\ &\text{3. ID/EX.RegisterRt} \neq 0 \quad (\text{not the zero register}) \end{align}

Why each condition matters:

Condition 1: Only loads create this hazard (stores don't write registers)
Condition 2: The register being loaded is actually used by the next instruction
Condition 3: MIPS $0 is hardwired to zero, so no real dependency exists

Implementing the Stall: Hardware Mechanism

The hazard detection unit sits between IF and ID stages. When it detects a load-use hazard:

Step 1: Prevent new instruction progress

Keep PC unchanged (don't increment)
Keep IF/ID register unchanged (re-read same instruction next cycle)

Step 2: Nullify the dependent instruction

Force all ID/EX control signals to 0
This makes the EX stage perform a NOP (no write, no memory access, no operation)

Step 3: Let earlier stages complete

MEM and WB stages proceed normally
After 1 cycle, the load's data is available for forwarding

Worked example Example 1: Basic Load-Use Hazard

lw   $2, 20($1)      # Load from memory into $2
add  $4, $2, $3 \quad \# \text{ Use}$2 immediately ← HAZARD!
sub  $5, $4, $6      \# Uses$4 (no hazard from load)

Why the hazard occurs:

lw produces $2 at the end of cycle 4 (MEM stage)
add starts its EX stage at the start of cycle 4 — too early
Forwarding needs the data to already exist; it doesn't yet

Stall insertion:

Hazard detected when add is in ID and lw is in EX
Insert 1 bubble: add stays in ID for one extra cycle
After stall, forward from lw MEM/WB → add EX

Cycle-by-cycle after stall:

Cycle:  1    2    3    4    5    6    7    8
lw      IF   ID   EX   MEM  WB
add          IF   ID   **   EX   MEM  WB          (** = stall/bubble; forwarded data used in EX cycle 5)
sub               IF   ID   **   EX   MEM  WB

Performance impact: This sequence has 3 real instructions (lw, add, sub). Without any hazard, three instructions finish in $3 + 4 = 7$ cycles in a 5-stage pipeline. With the one required stall they finish in 8 cycles. That single wasted cycle is the whole cost of the load-use hazard: $\text{extra cycles} = 1$ , i.e. an 8/7 ≈ 1.14× cycle count versus the ideal for this snippet.

Worked example Example 2: No Hazard — Intervening Instruction

lw   $2, 20($1)      # Load into $2
nop                  # Or any independent instruction
add  $4, $2, $3      \# Use$2 after delay

Why no stall needed:

lw completes MEM at end of cycle 4
nop occupies cycle 4 EX stage (does nothing)
add reaches EX in cycle 5
Forwarding from MEM/WB (available after cycle 4) → EX (cycle 5) works!

Compiler optimization: Smart compilers reorder code to place independent instructions after loads, avoiding stalls "for free."

Worked example Example 3: Load Followed by Store

lw  $2, 0($1)        # Load into $2
sw  $2, 4($1)        # Store $2 to memory ← NO HAZARD!

Why this step?

Pipeline the pair: lw has MEM in cycle 4; sw (one cycle behind) has MEM in cycle 5 (IF 2, ID 3, EX 4, MEM 5)
The store needs the value of $2 only in its MEM stage (cycle 5), when it writes the data to memory
lw produces $2 at the end of cycle 4 (MEM/WB), which is before cycle 5
So a MEM/WB → MEM forwarding path delivers $2 in time — no stall

Key insight: Stores consume their store-data register late in the pipeline (MEM stage), so they're more forgiving than ALU instructions that need it in EX.

Common Mistakes in Understanding Load-Use Hazards

Performance Impact: CPI Degradation

For an ideal 5-stage pipeline with no hazards, CPI = 1.0. Each load-use hazard adds 1 stall cycle:

\text{CPI}_{\text{pipeline}} = 1.0 + (\text{stall frequency}) \times 1

If 20% of instructions are loads and 50% of loads have immediate dependencies:

\text{CPI} = 1.0 + (0.20 \times 0.50) \times 1 = 1.10

This means 10% performance loss compared to an ideal pipeline.

Mitigation strategies:

Compiler scheduling: Reorder independent instructions to fill load delay slots
Out-of-order execution: Hardware dynamically reorders instructions (advanced processors)
Better caches: Faster memory reduces effective load latency (doesn't eliminate hazard, but improves overall CPI)

Recall Explain to a 12-year-old

Imagine you're making a sandwich assembly line with your friends:

Person A gets bread from the pantry (like lw loading from memory)
Person B is supposed to spread peanut butter on that bread immediately after The problem: Person A only brings the bread back at the very end of their turn, but Person B needs the bread at the very start of their turn — and their turns overlap! When Person B reaches the spreading station, Person A hasn't finished bringing the bread yet.

The solution: Person B has to wait (stall) at the spreading station doing nothing for one extra turn. Meanwhile, Person A finishes the pantry trip. Now when Person B finally spreads, the bread is ready.

A "forwarding path" is like Person A handing the bread directly to Person B instead of putting it on the table first — it saves time, but only if Person A already has the bread! We can't forward something that doesn't exist yet, so we must wait.

Connections

Data hazards and forwarding — Load-use is a special case forwarding can't fully solve
Pipeline control signals — Stalls force ID/EX control to zero
Hazard detection unit — Hardware that detects load-use conditions
Compiler instruction scheduling — Software technique to avoid stalls
Memory hierarchy and cache — Faster memory reduces load penalty
Five-stage MIPS pipeline — Architectural context for all hazards
Branch hazards and prediction — Control hazards also cause stalls

#flashcards/hardware

What is a load-use data hazard?

A hazard that occurs when an instruction immediately following a load depends on the loaded data. It requires a stall because the data isn't available until the end of the MEM stage, but the dependent instruction needs it at the start of its EX stage in the same cycle.

Why can't forwarding alone solve load-use hazards?

Forwarding can only route data that already exists. A load's data becomes available at the end of the MEM stage (cycle 4), but the next instruction needs it at the start of its EX stage (also cycle 4). Forwarding can't send data backwards in time.

What three conditions trigger a load-use stall?

1) ID/EX.MemRead = 1 (load in EX stage), 2) ID/EX.RegisterRt matches IF/ID.RegisterRs or RegisterRt (register dependency), 3) ID/EX.RegisterRt ≠ 0 (not the zero register).

How is a pipeline stall implemented in hardware?

1) Keep PC unchanged (don't fetch new instruction), 2) Keep IF/ID register unchanged (re-read same instruction), 3) Zero all ID/EX control signals (make EX stage a NOP), 4) Let MEM and WB stages proceed normally.

How many cycles does a load-use hazard stall cost?

Exactly 1 cycle. After the stall, forwarding from MEM/WB to EX bridges the remaining gap.

Why doesn't a load followed by a store create a hazard?

A store uses its source (store-data) register in the MEM stage (cycle 5 if it immediately follows the load), not the EX stage. The load produces its result by the end of cycle 4, so forwarding from MEM/WB to MEM works without a stall.

If 20% of instructions are loads and 40% of loads have immediate dependencies, what is the CPI?

CPI = 1.0 + (0.20 × 0.40) × 1 = 1.08. Each load-use stall adds 1 cycle, and they occur for 8% of all instructions.

What compiler optimization reduces load-use stalls?

Instruction scheduling — reordering code to place independent instructions after loads, filling the "load delay slot" with useful work instead of stalls.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, yaha pe baat samajhne wali ye hai ki jab hum lw (load word) instruction chalate hain, toh memory se data aane mein time lagta hai. Data MEM stage ke end mein ready hota hai (cycle 4 ke khatam pe), lekin jo next instruction hai — jaise add jo usi register ko use karta hai — usko wo data apne EX stage ke shuru mein chahiye hota hai, aur wo bhi cycle 4 mein hi. Matlab data available hone se pehle hi zaroorat pad jaati hai. Aur bhai, hum time mein peeche nahi ja sakte, yaani data ko backward forward nahi kar sakte! Isiliye ise load-use hazard kehte hain.

Ab yaha pe forwarding kaam nahi karti, jaisa ki normal ALU-to-ALU hazards mein karti hai. Kyunki forwarding tabhi kaam karti hai jab data pehle se exist karta ho — par yaha toh data abhi bana hi nahi hai! Isliye hardware ko ek stall ya bubble daalna padta hai, jo basically ek forced NOP (no-operation) hota hai. Ye ek cycle ka delay create karta hai — PC aur IF/ID register ko freeze kar dete hain, aur ID/EX ke control signals ko zero kar dete hain taaki EX stage kuch na kare. Ek cycle ruk jaane ke baad, load ka data ready ho jaata hai aur ab forwarding se aaram se pass ho jaata hai.

Ye cheez isliye important hai kyunki real processors mein ye stalls performance ko affect karte hain — har stall ka matlab ek wasted cycle. Compiler writers isiliye instructions ko smartly reorder karte hain taaki load ke turant baad dependent instruction na aaye, aur stall avoid ho jaaye. Exam ke point of view se bhi, tumhe wo teen stall detection conditions yaad rakhni chahiye: MemRead=1 (load hai), register match ho raha ho, aur register $0 na ho. Ye samajh lo toh pipelining ka poora hazard concept clear ho jaayega.

What is a Load-Use Hazard?

Why Forwarding Alone Fails for Loads

Implementing the Stall: Hardware Mechanism

Common Mistakes in Understanding Load-Use Hazards

Performance Impact: CPI Degradation

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Processor Datapath & Pipelining

Connections