Load-use hazard and stalls — Hinglish notes

5.2.7 · Hardware › Processor Datapath & Pipelining

Load-Use Hazard Kya Hota Hai?

Ek load-use data hazard tab hota hai jab load instruction ke bilkul baad wali instruction loaded data pe depend karti hai. ALU-ALU hazards ke unlike (jinhe forwarding solve kar leta hai), load hazards mein stall zaroori hai kyunki:

Load MEM stage mein complete hota hai (cycle 4 ka end)
Dependent instruction ko data apne EX stage ke START mein chahiye (bilkul agle instruction ke liye cycle 4 ka start)
Forwarding yeh gap bridge nahi kar sakti — data tab exist hi nahi karta jab zaroorat hoti hai (woh sirf cycle 4 ke end mein appear hota hai)

Sirf Forwarding Loads Ke Liye Kyun Fail Hoti Hai

The Timeline Problem:

Cycle:     1    2    3    4    5
lw  $2, 0($1)   IF   ID   EX   MEM  WB   ← data available END of cycle 4 (MEM)
add $4, $2, $3       IF   ID   EX   MEM  ← needs $2 START of cycle 4 (EX)

MEM/WB → EX forwarding ke saath bhi, add instruction ka EX stage cycle 4 ke start mein shuru hota hai, lekin load ka data cycle 4 ke end mein hi ready hota hai. Data tab exist hi nahi karta jab ALU ko chahiye.

1-cycle stall insert karne ke baad:

Cycle:     1    2    3    4    5    6
lw  $2, 0($1)   IF   ID   EX   MEM  WB
add $4, $2, $3       IF   ID  (stall) EX   MEM   ← add ek extra cycle ID mein ruka

Ab add cycle 5 mein EX execute karta hai. Load ka data (cycle 4 ke end mein available, MEM/WB mein held) MEM/WB → EX se cycle 5 mein forward hota hai. Perfect.

Stall Implement Karna: Hardware Mechanism

Hazard detection unit IF aur ID stages ke beech mein hoti hai. Jab woh load-use hazard detect karti hai:

Step 1: Nayi instruction ki progress rokna

PC ko unchanged rakhna (increment mat karo)
IF/ID register ko unchanged rakhna (agli cycle mein same instruction dobara read karo)

Step 2: Dependent instruction ko nullify karna

Saare ID/EX control signals ko 0 force karo
Isse EX stage ek NOP perform karta hai (no write, no memory access, no operation)

Step 3: Purani stages ko complete hone do

MEM aur WB stages normally proceed karti hain
1 cycle baad, load ka data forwarding ke liye available ho jaata hai

Worked example Example 1: Basic Load-Use Hazard

lw   $2, 20($1)      # Load from memory into $2
add  $4, $2, $3 \quad \# \text{ Use}$2 immediately ← HAZARD!
sub  $5, $4, $6      \# Uses$4 (no hazard from load)

Hazard kyun hota hai:

lw cycle 4 ke end mein $2 produce karta hai (MEM stage)
add cycle 4 ke start mein apna EX stage shuru karta hai — bahut jaldi
Forwarding ke liye data pehle se exist karna chahiye; abhi nahi karta

Stall insertion:

Hazard tab detect hota hai jab add ID mein hai aur lw EX mein hai
1 bubble insert karo: add ek extra cycle ID mein ruki rehti hai
Stall ke baad, lw MEM/WB → add EX se forward karo

Stall ke baad cycle-by-cycle:

Cycle:  1    2    3    4    5    6    7    8
lw      IF   ID   EX   MEM  WB
add          IF   ID   **   EX   MEM  WB          (** = stall/bubble; forwarded data used in EX cycle 5)
sub               IF   ID   **   EX   MEM  WB

Performance impact: Is sequence mein 3 real instructions hain (lw, add, sub). Bina kisi hazard ke, teen instructions ek 5-stage pipeline mein $3 + 4 = 7$ cycles mein finish hoti hain. Ek required stall ke saath woh 8 cycles mein finish hoti hain. Woh ek wasted cycle hi load-use hazard ki poori cost hai: $extra cycles = 1$ , yani is snippet ke liye ideal ke comparison mein 8/7 ≈ 1.14× cycle count.

Worked example Example 2: Koi Hazard Nahi — Beech Mein Instruction

lw   $2, 20($1)      # Load into $2
nop                  # Ya koi bhi independent instruction
add  $4, $2, $3      \# Use$2 after delay

Stall kyun nahi chahiye:

lw cycle 4 ke end mein MEM complete karta hai
nop cycle 4 EX stage occupy karta hai (kuch nahi karta)
add cycle 5 mein EX reach karta hai
MEM/WB se forwarding (cycle 4 ke baad available) → EX (cycle 5) kaam karta hai!

Compiler optimization: Smart compilers loads ke baad independent instructions reorder karte hain, bina kisi extra cost ke stalls avoid karte hain.

Worked example Example 3: Load ke Baad Store

lw  $2, 0($1)        # Load into $2
sw  $2, 4($1)        # Store $2 to memory ← NO HAZARD!

Yeh step kyun?

Pair ko pipeline karo: lw ka MEM cycle 4 mein hai; sw (ek cycle peeche) ka MEM cycle 5 mein hai (IF 2, ID 3, EX 4, MEM 5)
Store ko $2 ki value sirf apne MEM stage (cycle 5) mein chahiye, jab woh data memory mein likhta hai
lw cycle 4 ke end mein $2 produce karta hai (MEM/WB), jo cycle 5 se pehle hai
Toh ek MEM/WB → MEM forwarding path $2 time pe deliver kar deta hai — koi stall nahi

Key insight: Stores apna store-data register pipeline mein late consume karte hain (MEM stage), isliye woh ALU instructions se zyada forgiving hote hain jo EX mein data chahti hain.

Load-Use Hazards Samajhne Mein Common Mistakes

Performance Impact: CPI Degradation

Ek ideal 5-stage pipeline ke liye bina hazards ke, CPI = 1.0. Har load-use hazard 1 stall cycle add karta hai:

CPI_{pipeline} = 1.0 + (stall frequency) \times 1

Agar 20% instructions loads hain aur 50% loads mein immediate dependencies hain:

CPI = 1.0 + (0.20 \times 0.50) \times 1 = 1.10

Iska matlab 10% performance loss hai ek ideal pipeline ke comparison mein.

Mitigation strategies:

Compiler scheduling: Load delay slots fill karne ke liye independent instructions reorder karo
Out-of-order execution: Hardware dynamically instructions reorder karta hai (advanced processors)
Better caches: Faster memory effective load latency reduce karti hai (hazard eliminate nahi hota, lekin overall CPI improve hoti hai)

Recall Ek 12-saal ke bachche ko explain karo

Socho tum apne doston ke saath ek sandwich assembly line bana rahe ho:

Person A pantry se bread laata hai (jaise lw memory se load karta hai)
Person B ko chahiye ki woh us bread par turant peanut butter lagaye Problem: Person A bread apni turn ke bilkul end mein wapas laata hai, lekin Person B ko bread apni turn ke bilkul start mein chahiye — aur unki turns overlap karti hain! Jab Person B spreading station par pahunchta hai, Person A abhi bread lane ke kaam se return nahi kiya hota.

Solution: Person B ko spreading station par wait (stall) karna padta hai ek extra turn kuch nahi karte hue. Iss beech, Person A pantry trip finish karta hai. Ab jab Person B finally spread karta hai, bread ready hoti hai.

Ek "forwarding path" aise hai jaise Person A bread directly Person B ko hand kare instead of table par rakhne ke — isse time bachta hai, lekin tabhi kaam karta hai jab Person A ke paas bread pehle se ho! Hum kuch aisa forward nahi kar sakte jo exist hi nahi karta, toh hume wait karna padta hai.

Connections

Data hazards and forwarding — Load-use ek special case hai jise forwarding poori tarah solve nahi kar sakti
Pipeline control signals — Stalls ID/EX control ko zero force karti hain
Hazard detection unit — Hardware jo load-use conditions detect karta hai
Compiler instruction scheduling — Stalls avoid karne ki software technique
Memory hierarchy and cache — Faster memory load penalty reduce karti hai
Five-stage MIPS pipeline — Saare hazards ka architectural context
Branch hazards and prediction — Control hazards bhi stalls cause karte hain

#flashcards/hardware

Load-use data hazard kya hota hai?

Ek hazard jo tab hota hai jab load ke bilkul baad wali instruction loaded data pe depend karti hai. Isme stall zaroori hai kyunki data MEM stage ke end tak available nahi hota, lekin dependent instruction ko woh usi cycle mein apne EX stage ke start mein chahiye.

Forwarding akele load-use hazards kyun solve nahi kar sakti?

Forwarding sirf woh data route kar sakti hai jo pehle se exist karta ho. Load ka data MEM stage ke end mein available hota hai (cycle 4), lekin agle instruction ko woh apne EX stage ke start mein chahiye (bhi cycle 4). Forwarding data ko time mein ulta nahi bhej sakti.

Kaun si teen conditions load-use stall trigger karti hain?

1) ID/EX.MemRead = 1 (EX stage mein load hai), 2) ID/EX.RegisterRt, IF/ID.RegisterRs ya RegisterRt se match karta hai (register dependency), 3) ID/EX.RegisterRt ≠ 0 (zero register nahi hai).

Hardware mein pipeline stall kaise implement hoti hai?

1) PC unchanged rakho (nayi instruction fetch mat karo), 2) IF/ID register unchanged rakho (same instruction dobara read karo), 3) Saare ID/EX control signals zero karo (EX stage ko NOP banao), 4) MEM aur WB stages normally proceed karti rahein.

Load-use hazard stall kitne cycles cost karti hai?

Exactly 1 cycle. Stall ke baad, MEM/WB se EX pe forwarding remaining gap bridge kar deti hai.

Load ke baad store hazard kyun create nahi karta?

Ek store apna source (store-data) register MEM stage mein use karta hai (cycle 5 agar woh load ke bilkul baad aaye), EX stage mein nahi. Load apna result cycle 4 ke end tak produce kar deta hai, toh MEM/WB se MEM pe forwarding bina stall ke kaam karti hai.

Agar 20% instructions loads hain aur 40% loads mein immediate dependencies hain, toh CPI kya hai?

CPI = 1.0 + (0.20 × 0.40) × 1 = 1.08. Har load-use stall 1 cycle add karta hai, aur woh saari instructions ke 8% ke liye hoti hain.

Kaun si compiler optimization load-use stalls reduce karti hai?

Instruction scheduling — code ko reorder karna taaki loads ke baad independent instructions aayein, "load delay slot" ko stalls ki jagah useful kaam se fill kiya jaaye.