Everything in the parent note (Load-use hazard and stalls) rests on a handful of ideas: what a pipeline is, what the five stages do, what a register and memory are, and what cycles and stages mean on a timeline. We build each from zero, in an order where every new symbol only uses words already earned.
Before anything moves, we need a drumbeat. A processor has a clock: a signal that ticks on and off, on and off, forever, at a steady rate.
The picture: think of a metronome. Every "tick" = one cycle. Nothing in the processor moves between ticks; work is snapped forward exactly on each tick.
Why the topic needs it: the whole load-use hazard story is a story about timing — "the data is ready at the end of cycle 4 but is needed at the start of cycle 4." The word "cycle" is the ruler we measure everything against.
Data has to be somewhere. There are two somewheres, and the difference between them is the beating heart of this whole topic.
The picture: a register is a pen already in your hand; memory is a book on a shelf across the room. Grabbing the pen is instant; walking to the shelf costs time.
Why the topic needs it: a load (lw) is exactly the act of walking to the shelf (memory) and bringing a value back into your hand (a register). Because the shelf is far, the value arrives late — and that lateness is the hazard.
An instruction is one command, like "add these two numbers" or "load this value." Each instruction names the registers it touches. Three names appear again and again:
Why the topic needs it: a hazard is detected by comparing register names: "does the next instruction read the same register this load is about to fill?" Those names are Rs, Rt, Rd. Full detail lives in Hazard detection unit.
Every MIPS instruction is broken into five smaller jobs, done in order. This is the Five-stage MIPS pipeline.
The picture: an instruction is a car on an assembly line moving through five workstations, left to right, one station per cycle.
Why the topic needs it: the load's value is produced in MEM and a following add needs it in EX. The whole hazard is "MEM finishes after EX starts." You cannot see that unless you know which stage does what.
One instruction alone would waste four stations at any moment. So we pipeline: start a new instruction every cycle, each one step behind the last.
The picture below is the key diagram of the whole chapter — read the diagonal: instruction 2 always trails instruction 1 by exactly one cycle.
Why the topic needs it: because instructions run at the same time, one instruction's result may not be finished when the next one wants it. That overlap is what creates the possibility of a hazard.
Each foundation feeds the next: cycles and stages define when things happen, registers and memory define where data lives, pipelining makes them overlap, overlap creates dependencies, and the load's slowness turns one dependency into the hazard that only a stall (plus forwarding) can cure.