Parent note (Load-use hazard and stalls) mein jo kuch bhi hai, woh kuch basic ideas pe tika hai: pipeline kya hota hai, five stages kya karte hain, register aur memory kya hain, aur timeline pe cycles aur stages ka kya matlab hai. Hum inhe zero se build karte hain, ek aisi order mein jahan har naya symbol sirf pehle se samjhe hue words use karta hai.
Kuch bhi move karne se pehle, hume ek drumbeat chahiye. Ek processor mein ek clock hoti hai: ek signal jo on-off, on-off, hamesha steady rate pe tick karta rehta hai.
Picture: ek metronome socho. Har "tick" = ek cycle. Processor mein kuch bhi ticks ke beech move nahi hota; kaam exactly har tick pe aage snap hota hai.
Yeh topic isko kyun chahiye: poora load-use hazard ka story timing ki kahani hai — "data cycle 4 ke end pe ready hota hai lekin cycle 4 ke start pe chahiye hota hai." "Cycle" woh ruler hai jisse hum sab kuch measure karte hain.
Data kahi na kahi hona chahiye. Do jagah hain, aur unke beech ka farq is poore topic ki dhadkan hai.
Picture: register ek pen hai jo pehle se haath mein hai; memory ek book hai jo kamre ke doosri taraf shelf pe hai. Pen pakadna instant hai; shelf tak jaana time leta hai.
Yeh topic isko kyun chahiye: ek load (lw) exactly shelf (memory) tak jaane aur ek value haath (ek register) mein wapas laane ka kaam hai. Kyunki shelf door hai, value late aati hai — aur wahi lateness hazard hai.
Ek instruction ek command hai, jaise "yeh do numbers add karo" ya "yeh value load karo." Har instruction unhe touch karne wale registers ke naam batati hai. Teen naam baar baar aate hain:
Yeh topic isko kyun chahiye: hazard detect karne ke liye register names compare ki jaati hain: "kya agla instruction wahi register read karta hai jo yeh load fill karne wala hai?" Woh names hain Rs, Rt, Rd. Poori detail Hazard detection unit mein hai.
Har MIPS instruction paanch chhoti jobs mein tooti hoti hai, order mein ki jaati hain. Yeh hai Five-stage MIPS pipeline.
Picture: ek instruction ek assembly line pe car hai jo paanch workstations se left se right, ek station per cycle move karti hai.
Yeh topic isko kyun chahiye: load ki value MEM mein produce hoti hai aur agla add use EX mein chahiye. Poora hazard hai "MEM finishes after EX starts." Yeh tab tak nahi dikhta jab tak pata na ho ki kaun sa stage kya karta hai.
Akela ek instruction kisi bhi moment mein chaar stations waste kar dega. To hum pipeline karte hain: har cycle mein ek naya instruction start karo, har ek pichle se ek step peeche.
Neeche di gai picture poore chapter ki key diagram hai — diagonal padho: instruction 2 hamesha instruction 1 se exactly ek cycle peeche rehta hai.
Yeh topic isko kyun chahiye: kyunki instructions ek saath chalti hain, ek instruction ka result tab tak finish nahi hua hota jab agla usse chahiye. Woh overlap hi hazard ki possibility create karta hai.
Har foundation agla feed karta hai: cycles aur stages define karte hain kab cheezein hoti hain, registers aur memory define karte hain kahan data rehta hai, pipelining unhe overlap karta hai, overlap dependencies create karta hai, aur load ki slowness ek dependency ko us hazard mein badal deti hai jise sirf stall (plus forwarding) theek kar sakta hai.
Rt — load ke liye, Rt woh destination register hai jisme value jaati hai.
Kaun se stage mein load apni value produce karta hai?
MEM (MEM stage ke end pe available).
Kaun se stage mein ek add ko apni source values chahiye?
EX (Execute stage ke start pe).
Forwarding kya nahi kar sakta?
Data ko time mein peeche move nahi kar sakta — yeh sirf data ko stages ke beech space mein move karta hai.
Ek stall plus forwarding load-use hazard kyun fix karta hai?
Stall ek cycle ki delay create karta hai taaki value exist kare; phir forwarding MEM/WB data ko EX tak pahunchata hai. Forwarding ke bina do stalls chahiye honge.