Energy efficiency (performance per watt): Worked examples

Before we start, one reminder of the symbols we lean on (all built in the parent — nothing new is assumed):

Related builds: Dynamic vs Static Power, DVFS - Dynamic Voltage and Frequency Scaling, Leakage Current and Temperature, Multicore and Parallelism, FLOPS and Benchmarking, Thermal Design Power (TDP), Dennard Scaling.

The scenario matrix

Every question this topic throws is one (or a blend) of these cells. Each worked example below is tagged with the cell it lands on.

Cell	The situation	The trap / limiting behaviour
C1	Straight perf/watt from raw numbers	Getting the units to be ops per joule
C2	Compare two chips, different speed and power	Faster ≠ more efficient
C3	Voltage-only scaling ( $f$ fixed)	Power is quadratic in $V$ , not linear
C4	Joint $V$ – $f$ scaling (DVFS, $f \propto V$ )	Power $\sim f^{3}$ , perf/watt $\sim 1/ f^{2}$
C5	Dynamic + leakage together	Leakage doesn't shrink with $V^{2}$ the same way
C6	Degenerate: zero leakage / leakage-dominated	Which term vanishes, which dominates
C7	Race-to-idle word problem (total energy, not power)	energy = power × time can rise when you speed up
C8	Multicore vs single fast core (exam twist)	many slow cores beat one hot core on perf/watt
C9	Limiting case: $f \to 0$ and $f \to \infty$	leakage floor at low $f$ , cube wall at high $f$

We now hit every cell.

Figure — Energy efficiency (performance per watt)

The figure above is the map: performance rises linearly with $f$ (yellow), power rises like $f^{3}$ (red), so their ratio — perf/watt (green) — falls like $1/ f^{2}$ . Keep glancing back at it; almost every example lives somewhere on these curves.

C1 — Straight perf/watt from raw numbers

Worked example Example 1 · Cell C1

A CPU sustains $500 GFLOPS$ while drawing $125 W$ . Find perf/watt and energy per FLOP.

Forecast: Guess the perf/watt in GFLOPS/W and whether energy-per-op will be in the picojoule or nanojoule range.

Divide performance by power. $\frac{500 \times 1 0 ^{9} FLOP/s}{125 W} = 4 \times 1 0^{9} \frac{FLOP}{s\cdotW} = 4 GFLOPS/W .$ Why this step? Perf/watt is literally the division; because $1 W = 1 J/s$ , the "per second" on top and bottom cancel, leaving FLOP per joule.
Take the reciprocal for energy per FLOP. $\frac{1}{4 \times 1 0 ^{9} FLOP/J} = 2.5 \times 1 0^{- 10} J/FLOP = 250 pJ/FLOP .$ Why this step? Ops-per-joule inverted gives joules-per-op — the honest cost of one operation.

Verify: Multiply back: $4 \times 1 0^{9} FLOP/J \times 2.5 \times 1 0^{- 10} J/FLOP = 1$ ✓ (dimensionless, as a reciprocal pair must be). And $4 GFLOPS/W \times 125 W = 500 GFLOPS$ ✓ recovers the original speed.

C2 — Compare two chips (faster ≠ better)

C3 — Voltage-only scaling (the quadratic trap)

C4 — Joint V–f scaling (the cube law)

Worked example Example 4 · Cell C4

Under DVFS the voltage and frequency move together, $f \propto V$ . We raise the clock from $2.0 GHz$ to $3.0 GHz$ . Find the factor change in dynamic power and in perf/watt.

Forecast: A 1.5× clock. Guess the power multiplier — is it near 1.5, near 2.25, or bigger?

Frequency ratio. $\frac{f _{new}}{f _{old}} = \frac{3.0}{2.0} = 1.5.$ Why this step? All other factors are pinned to this ratio through $f \propto V$ .
Power scales like $f^{3}$ . Since $V \propto f$ , $P_{dyn} \propto V^{2} f = f^{2} \cdot f = f^{3}$ : $\frac{P _{new}}{P _{old}} = 1. 5^{3} = 3.375.$ Why this step? The clock drags voltage up with it, so you pay $f^{2}$ from the voltage and $f$ from the switching rate.
Perf/watt scales like $1/ f^{2}$ . Performance $\propto f$ , so $\frac{( Perf/W ) _{new}}{( Perf/W ) _{old}} = \frac{f}{f ^{3}} = \frac{1}{f ^{2}} = \frac{1}{1. 5 ^{2}} = 0.444.$ Why this step? Perf/watt = perf ÷ power = $f / f^{3}$ .

Verify: Check consistency: perf ratio $= 1.5$ , power ratio $= 3.375$ , so perf/watt ratio $= 1.5/3.375 = 0.4 \overline{4}$ ✓, matching $1/1. 5^{2}$ . Speeding up 50% cost you 56% of your efficiency — exactly the $1/ f^{2}$ collapse on the green curve of the map figure.

C5 — Dynamic + leakage together

Worked example Example 5 · Cell C5

A core at $V = 1.0 V$ has $P_{dyn} = 8 W$ and leaks $I_{leak} = 2 A$ , so $P_{static} = V I_{leak} = 2 W$ . We apply DVFS: $V \to 0.8 V$ , $f \to 0.8 \times$ (so $f \propto V$ ), and (approximately) $I_{leak}$ stays $2 A$ . Find the new total power.

Forecast: Dynamic power will shrink a lot; leakage barely changes. Guess whether total drops more or less than the 51% we'd get from dynamic alone.

New dynamic power ( $\propto V^{2} f$ , both fall to 0.8×). $P_{dyn,new} = 8 \times (0.8)^{2} \times 0.8 = 8 \times 0.512 = 4.096 W .$ Why this step? Same cube-ish scaling as before, but now applied to a real absolute value.
New static power ( $= V I_{leak}$ , only $V$ changes). $P_{static,new} = 0.8 \times 2 = 1.6 W .$ Why this step? Leakage scales linearly with $V$ (through $V I_{leak}$ ), not quadratically — it stubbornly refuses to fall as fast.
Add. $P_{total,new} = 4.096 + 1.6 = 5.696 W$ (was $8 + 2 = 10 W$ ). Why this step? Total power is the sum; the two terms respond to $V$ differently, so you must scale them separately.

Verify: Total ratio $= 5.696/10 = 0.5696$ . Dynamic-only ratio was $0.512$ ; because the "sticky" leakage falls only to $0.8$ , the total drops less (57%) than dynamic alone (51%) ✓ — leakage always dilutes the DVFS win.

C6 — Degenerate: zero leakage vs leakage-dominated

Worked example Example 6 · Cell C6

Take the two limiting worlds for a $10 W$ chip and predict the DVFS outcome for the same $V \to 0.8 \times$ , $f \to 0.8 \times$ move. (a) Ideal old node: all $10 W$ is dynamic, leakage $= 0$ . (b) Leaky deep-nanometer node: all $10 W$ is leakage, dynamic $\approx 0$ .

Forecast: In which world does DVFS help more?

World (a), pure dynamic. $10 \times (0.8)^{2} \times 0.8 = 10 \times 0.512 = 5.12 W$ . Why this step? With leakage exactly zero the $P_{static}$ term vanishes — the cube law rules unopposed.
World (b), pure leakage. $10 \times 0.8 = 8.0 W$ . Why this step? With dynamic $\approx 0$ , only $V I_{leak}$ survives; it scales linearly with $V$ , so only a modest drop.
Compare. DVFS cuts world (a) to 51% but world (b) only to 80%. Why this step? The degenerate cases isolate each mechanism, showing DVFS is a dynamic-power lever — it barely touches leakage.

Verify: $0. 8^{3} = 0.512$ ✓ and $0. 8^{1} = 0.8$ ✓. These bracket the mixed Example 5 result of $0.5696$ , which sat between $0.512$ and $0.8$ ✓ exactly as a weighted blend of the two extremes should.

C7 — Race-to-idle (total energy, not power)

Worked example Example 7 · Cell C7

A task needs $6 \times 1 0^{12}$ operations. Choose one of two run modes: Fast: $3 GHz$ -equivalent, sustains $3 \times 1 0^{12} ops/s$ at $60 W$ . Slow: $2 GHz$ -equivalent, sustains $2 \times 1 0^{12} ops/s$ at $24 W$ . Which finishes using less total energy?

Forecast: "Fast finishes sooner, so it should idle earlier and win." True or a trap?

Time for each mode ( $t = work / throughput$ ). $t_{fast} = \frac{6 \times 1 0 ^{12}}{3 \times 1 0 ^{12}} = 2 s, t_{slow} = \frac{6 \times 1 0 ^{12}}{2 \times 1 0 ^{12}} = 3 s .$ Why this step? Energy is power × time, so we need the time, not just the speed.
Energy for each mode ( $E = P \cdot t$ ). $E_{fast} = 60 \times 2 = 120 J, E_{slow} = 24 \times 3 = 72 J .$ Why this step? This is the honest metric — joules to finish the fixed job.
Compare. Slow uses 72 J vs fast's 120 J → slow wins by 48 J (40% less energy). Why this step? Even though fast finished 1 s sooner, its power was 2.5× higher, and time only fell 1.5×. Power won the fight.

Verify (via perf/watt): Fast $= 3 \times 1 0^{12} /60 = 5 \times 1 0^{10}$ ops/J; slow $= 2 \times 1 0^{12} /24 = 8.33 \times 1 0^{10}$ ops/J. Energy = work ÷ (ops/J): fast $= 6 \times 1 0^{12} /5 \times 1 0^{10} = 120 J$ ✓, slow $= 6 \times 1 0^{12} /8.33 \times 1 0^{10} = 72 J$ ✓. Both routes agree — race-to-idle lost here.

C8 — Multicore vs one hot core (exam twist)

Worked example Example 8 · Cell C8

You need $4 \times 1 0^{12} ops/s$ . Two ways: One hot core: push a single core to hit all $4 \times 1 0^{12} ops/s$ ; because $f \propto V$ , its power scales like $f^{3}$ . A baseline core does $1 \times 1 0^{12} ops/s$ at $5 W$ . Four cool cores: four baseline cores each at $1 \times 1 0^{12} ops/s$ , $5 W$ , run in parallel.

Forecast: Same total throughput — but which draws less power?

Four cool cores. Throughput adds, power adds: $P_{multi} = 4 \times 5 = 20 W for 4 \times 1 0^{12} ops/s .$ Why this step? Parallelism gets speed by adding units at the efficient point, not by pushing one unit up the cube.
One hot core must be $4 \times$ faster, i.e. $f \to 4 \times$ , so $P \propto f^{3}$ : $P_{hot} = 5 \times 4^{3} = 5 \times 64 = 320 W .$ Why this step? A single core reaching $4 \times$ throughput climbs the $f^{3}$ wall — the punishing region on the red curve.
Compare. $20 W$ vs $320 W$ for identical work → multicore is 16× more efficient here. Why this step? This is why the industry went multicore instead of chasing ever-higher clocks.

Verify: Perf/watt: multi $= 4 \times 1 0^{12} /20 = 2 \times 1 0^{11}$ ops/(s·W); hot $= 4 \times 1 0^{12} /320 = 1.25 \times 1 0^{10}$ . Ratio $= 2 \times 1 0^{11} /1.25 \times 1 0^{10} = 16$ ✓, matching the power ratio $320/20 = 16$ ✓ (throughput was equal, so perf/watt ratio = inverse power ratio).

C9 — Limiting cases: $f \to 0$ and $f \to \infty$

Worked example Example 9 · Cell C9

A core has $P_{static} = 2 W$ (fixed leakage floor) and $P_{dyn} = k f^{3}$ with $k$ chosen so that at $f = 2 GHz$ the dynamic power is $8 W$ . Examine both extremes of clock speed for perf/watt (perf $\propto f$ ).

Forecast: Where does the efficiency curve peak — very slow, very fast, or somewhere in the middle?

Find $k$ . $8 = k (2)^{3} = 8 k \Rightarrow k = 1$ (with $f$ in GHz, power in W). Why this step? Anchoring the constant lets us evaluate any $f$ .
Low-frequency limit $f \to 0$ . $P_{dyn} = f^{3} \to 0$ , so $P_{total} \to P_{static} = 2 W$ , while perf $\propto f \to 0$ . Perf/watt $\propto f / (2 + f^{3}) \to f /2 \to 0$ . Why this step? At a crawl you still pay the constant $2 W$ leakage but do almost no work — leakage floor kills efficiency at very low $f$ .
High-frequency limit $f \to \infty$ . $P_{total} \approx f^{3}$ dominates, perf/watt $\propto f / f^{3} = 1/ f^{2} \to 0$ . Why this step? The cube wall kills efficiency at very high $f$ .
So the peak is in the middle. Efficiency $E (f) = f / (2 + f^{3})$ . Maximise: $E^{'} (f) = 0 \Rightarrow (2 + f^{3}) - f (3 f^{2}) = 0 \Rightarrow 2 - 2 f^{3} = 0 \Rightarrow f = 1 GHz$ . Why this step? Setting the derivative to zero finds where rising work stops outpacing rising power — the sweet spot the parent note promised.

Verify: At $f = 1$ : $E = 1/ (2 + 1) = 1/3 \approx 0.333$ . At $f = 0.5$ : $E = 0.5/ (2 + 0.125) = 0.235$ . At $f = 2$ : $E = 2/ (2 + 8) = 0.20$ . Both neighbours are lower than $0.333$ ✓ — confirming $f = 1 GHz$ is a genuine maximum, and both limits $\to 0$ ✓.

Recall Which cell was which?

What makes C7 (race-to-idle) different from C2 (chip compare)? ::: C7 fixes the total work and asks for energy = power × time, so a shorter run can still cost more; C2 compares steady-state perf/watt at unequal throughputs. In C6, why does the pure-leakage world barely improve under DVFS? ::: Leakage power is $V I_{leak}$ — linear in $V$ — so an $0.8 \times$ voltage gives only an $0.8 \times$ power cut, versus $0.512 \times$ for dynamic. In C9, why isn't the fastest clock the most efficient? ::: perf $\propto f$ but power $\propto f^{3}$ (plus a leakage floor), so perf/watt $\propto 1/ f^{2}$ collapses at high $f$ and the leakage floor kills it at low $f$ — the peak sits in the middle.

Active recall

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