Exercises — Energy efficiency (performance per watt)

WHAT: Performance per watt is just performance divided by power. WHY: The definition $\frac{\text{Perf}}{\text{Power}}$ fuses the two numbers into one honest score. $\frac{40\text{GFLOPS}}{20\text{W}}=2\text{GFLOPS/W}.$ Answer: $2\text{GFLOPS/W}$.

$P_{\text{dyn}}=\alpha C{V}^{2}f.$

• $\alpha$ = activity factor (fraction of gates flipping),
• $C$ = switched capacitance,
• $V$ = supply voltage (appears squared — this matters later),
• $f$ = clock frequency. Mnemonic from the parent: "Alpha Cats Voltage-Squared Frequency."

Operations per joule. Performance is work-per-second and power is energy-per-second; the "per second" cancels: $\frac{\text{work}/\text{s}}{\text{energy}/\text{s}}=\frac{\text{work}}{\text{energy}}=\frac{\text{ops}}{\text{joule}}.$ So perf/watt tells you the total work squeezable from a fixed energy budget (a battery).

(a) First divide performance by power: $\frac{60\times 10^{12}\text{FLOP/s}}{300\text{W}}=2\times 10^{11}\text{FLOP/(s⋅W)}.$ Now convert to the requested GFLOPS/W. The prefix "G" (giga) means $10^9$, so $1\text{GFLOPS/W}=10^9\text{FLOP/(s⋅W)}$. To express our number in those units we divide by $10^9$: $2\times 10^{11}\text{FLOP/(s⋅W)}=\frac{2\times 10^{11}}{10^9}\text{GFLOPS/W}=200\text{GFLOPS/W}.$ (b) Energy per FLOP is the reciprocal of ops-per-joule (note FLOP/(s·W) = FLOP/J): $\frac{1}{2\times 10^{11}\text{FLOP/J}}=5\times 10^{-12}\text{J}=5\text{pJ/FLOP}.$ WHY the reciprocal: ops/joule flipped upside-down gives joules/op — confirming perf/watt ≡ work/energy.

WHAT: We only need relative factors, so plug ratios into $P_{\text{dyn}}\propto V^{2}f$. ${\left(\frac{0.9}{1.2}\right)}^2\times \frac{2.25}{3}=(0.75{)}^2\times 0.75=0.5625\times 0.75=0.4218\dots$ Answer: $\approx 0.4219$, i.e. about $42.2\%$ of the original dynamic power. WHY: $\alpha$ and $C$ are unchanged, so they cancel in the ratio — only $V^{2}f$ moves.

Recall $I_{\text{leak}}$ is the always-on trickle current from the cast of symbols. Static power is just that current pushed by the voltage: $P_{\text{stat}}=V{I}_{\text{leak}}=1.0\times 2=2\text{W}.$ Total $=P_{\text{dyn}}+P_{\text{stat}}=8+2=10\text{W}$. Leakage share $=\frac{2}{10}=20\%$. This is why "only dynamic power matters" is false in deep-nanometer chips.

A: $120/48=2.5\text{GFLOPS/W}$. B: $200/100=2.0\text{GFLOPS/W}$. Efficiency: A wins ($2.5>2.0$) — more work per joule. Speed: B wins ($200>120$ GFLOPS raw). Not the same answer. Faster ≠ more efficient. For a battery/thermal-limited device pick A; for raw throughput where power is free, pick B. In the figure above, B's orange (speed) bar is taller, but its teal (perf/watt) bar is shorter than A's — remember the teal bars are both ×50 for visibility, so it's their relative height that carries the message, and A's teal is genuinely taller.

WHY $1/f^2$: performance $\propto f$, but under $V\propto f$ scaling power $\propto f^3$, so perf/watt $\propto f/f^3=1/f^2$. $\frac{1}{1.25^2}=\frac{1}{1.5625}=\mathrm{0.64.}$ Perf/watt falls to $64\%$ of its original value — a $36\%$ drop for a mere $25\%$ speed gain. That asymmetry is why clock-only scaling died and we moved to multicore.

WHAT: Total energy = power × time.

• X: $60\text{W}\times 10\text{s}=600\text{J}$.
• Y: $30\text{W}\times 16\text{s}=480\text{J}$. Y uses less energy ($480<600\text{J}$), even though it's slower. WHY the fast one lost: X needed higher $V$ and $f$; power ($\propto V^{2}f$) rose faster than the time fell. Finishing sooner does not guarantee less energy.

New dynamic: ratio $=(0.8{)}^2\times (1.6/2.0)=0.64\times 0.8=0.512$. $P_{\text{dyn}}^{\prime }=10\times 0.512=5.12\text{W}.$ New static: $P_{\text{stat}}=V{I}_{\text{leak}}$ (with $I_{\text{leak}}$ the fixed leakage current from the cast of symbols), and $V$ dropped by $0.8$: $P_{\text{stat}}^{\prime }=2\times 0.8=1.6\text{W}.$ New total: $5.12+1.6=6.72\text{W}$ (was $12\text{W}$). Performance tracks $f$: ratio $=1.6/2.0=0.8$. Perf/watt improvement $=\frac{\text{perf ratio}}{\text{power ratio}}=\frac{0.8}{6.72/12}=\frac{0.8}{0.56}=1.4286$. WHY only $V^{2}f$ moves for dynamic: $P_{\text{dyn}}=\alpha C{V}^{2}f$. Here $\alpha$ (activity) and $C$ (the fixed silicon capacitance) do not change under DVFS — the same gates switch on the same transistors — so they appear identically in the "before" and "after" and cancel when we take the ratio. Only $V$ and $f$ actually move, leaving $V^{2}f$. WHY static scales only as $V$: $P_{\text{stat}}=V{I}_{\text{leak}}$, and with $I_{\text{leak}}$ held constant here, static power is linear in $V$ — one factor of $V$, not squared — so it shrinks less aggressively than dynamic. Answer: total power $6.72\text{W}$; perf/watt up by $\approx 42.9\%$ for only $20\%$ less speed. Note leakage dilutes the pure-dynamic gain (compare Ex. 2.2's $56\%$ where leakage was ignored).

Throughput check (cores × frequency): single = $1\times 3\text{GHz}=3.0$; dual = $2\times 1.5\text{GHz}=3.0$. Equal throughput. ✓ WHY $\alpha C$ cancels again: every core is the same silicon design, so $\alpha$ and $C$ are identical across all cores and across both options — they factor out of the comparison, leaving each core's dynamic power $\propto V^{2}f$. Single-core dynamic ($V=1.0$, $f=3$): $\propto 1.0^2\times 3=3.0$ (units of $\alpha C\cdot V^{2}f$). Two-core dynamic ($V=0.75$, $f=1.5$, two cores): $2\times (0.75^2\times 1.5)=2\times (0.5625\times 1.5)=2\times 0.84375=\mathrm{1.6875.}$ Ratio $=1.6875/3.0=0.5625$. Answer: same throughput at $\approx 56.25\%$ of the dynamic power — the multicore win, straight from $V^2$. Two slow cores beat one fast core because each runs at lower voltage.

Set up total power as a function of $V$. Substitute $f=2V$: $P(V)=0.5\cdot V^2\cdot (2V)+V\cdot 1.0=V^3+V.$ Cap at 5 W: solve $V^3+V=5$. Try $V=1.5$: $3.375+1.5=4.875$ (just under). Try $V=1.52$: $3.511+1.52=5.03$. So $V\approx 1.5157\text{V}$ — comfortably above $V_{\text{th}}$, so the simple model is valid here. $V^{\ast }\approx 1.5157\text{V}\Rightarrow f=2V\approx 3.031\text{GHz}.$ Perf/watt. Performance $\propto f$, and by the stated one-op-per-tick assumption $f=3.031\text{GHz}$ corresponds to $3.031\text{GFLOPS}$; power is $5\text{W}$ at the cap: $\frac{3.031\text{GFLOPS}}{5\text{W}}\approx 0.606\text{GFLOPS/W}.$ WHY it matters: the cube term $V^3$ dominates near the ceiling — squeezing the last MHz costs disproportionate power, exactly why phones throttle. Answer: $f\approx 3.03\text{GHz}$, perf/watt $\approx 0.61\text{GFLOPS/W}$.

WHAT we optimise: perf/watt $=\frac{2V}{V^3+V}=\frac{2}{V^2+1}$ (cancel one $V$). WHY the derivative tool: to find the maximum of a smooth function we ask where its slope is zero — that's what a derivative finds. $\frac{d}{dV}\left(\frac{2}{V^2+1}\right)=\frac{-2\cdot 2V}{(V^2+1{)}^2}=\frac{-4V}{(V^2+1{)}^2}.$ This is negative for all $V>0$ and zero only at $V=0$: efficiency $\frac{2}{V^2+1}$ monotonically decreases as $V$ rises. So within this simple model the theoretical peak sits at the lowest possible voltage ($V\to 0^{+}$, efficiency $\to 2$). WHY real chips don't sit there — three reasons:

1. Frequency dies. $f=2V\to 0$, so the chip becomes maximally efficient but does almost no work per second — it can never meet a deadline. Efficiency (ops/joule) and usefulness (ops/second) pull in opposite directions.
2. The model breaks below $V_{\text{th}}$. Once $V$ approaches the threshold voltage, transistors enter the subthreshold region: $f\propto V$ no longer holds (speed collapses faster than linearly) and the constant-$I_{\text{leak}}$ assumption fails — leakage rises exponentially, so $P_{\text{stat}}$ per unit work explodes rather than shrinking. The pretty $2/(V^2+1)$ curve simply is not valid there.
3. Leakage per second is fixed overhead. Dragging a job out at low $f$ keeps the chip powered for longer, and $P_{\text{stat}}=V{I}_{\text{leak}}$ drains energy every second it's on — so beyond a point lowering voltage can raise total energy for a fixed task. Conclusion: real design targets the ==lowest voltage that still meets the performance deadline and stays safely above $V_{\text{th}}$== — a constrained optimum, never the mathematical $V\to 0$ peak.

Energy = power × time, summed over nodes.

• P: $4\times 250\text{W}\times 2\text{h}=2000\text{Wh}=2.0\text{kWh}$.
• Q: $8\times 150\text{W}\times 1.5\text{h}=1800\text{Wh}=1.8\text{kWh}$. Energy winner: Q ($1.8<2.0\text{kWh}$). Time winner: Q too ($1.5\text{h}<2\text{h}$). Here Q wins on both — the low-clock nodes (lower $V$, so $V^2$ savings) more than pay for the extra nodes. Trade-off statement: wide-and-slow (more nodes at lower voltage) usually beats narrow-and-fast on energy, and here even on time because 8 nodes parallelise the work; the only cost Q pays is higher up-front hardware and more total idle/static power (8 chips each leak $V{I}_{\text{leak}}$ whenever they idle), which is the reliability and capital-cost dimension the pure energy sum quietly hides. So: pick Q for this job, but if node cost or leakage-at-idle dominated your budget, the comparison could flip.