Energy efficiency (performance per watt): Question bank

This bank leans on ideas from Dynamic vs Static Power, DVFS - Dynamic Voltage and Frequency Scaling, Dennard Scaling, Thermal Design Power (TDP), Leakage Current and Temperature, Multicore and Parallelism, and FLOPS and Benchmarking. Every symbol here was defined in the parent note: $P$ = power (watts = joules/sec), $V$ = supply voltage, $f$ = clock frequency, $C$ = switching capacitance, $α$ = activity factor, $I_{leak}$ = leakage current.

True or false — justify

A faster chip always finishes a task using less total energy

False — energy = power × time; the higher

f

needs a higher

V

and

P \propto V^{2} f

, so power can climb faster than time falls, raising total energy despite the shorter runtime.

Performance per watt has the same information as "operations per joule"

True — the "per second" in performance (work/sec) and in power (energy/sec) cancel, leaving work/energy = operations/joule.

Halving the supply voltage halves dynamic power

False — dynamic power is

α C V^{2} f

, quadratic in

V

; halving

V

(at fixed

f

) cuts dynamic power to a quarter, not a half.

Doubling clock frequency at fixed voltage only doubles dynamic power

True if $V$ is genuinely held fixed —

f

is linear in

P_{dyn}

. The cube law only appears when raising

f

forces a higher

V

A chip with higher raw FLOPS is automatically the more energy-efficient choice

False — efficiency is FLOPS ÷ watts; a faster chip drawing disproportionately more power can score lower perf/watt (see the parent's Chip A vs Chip B).

Leakage (static) power can be safely ignored in modern deep-nanometer chips

False — at small nodes leakage becomes a large slice of total power and rises with temperature, so ignoring it breaks the thermal and reliability budget.

Perf/watt scaling as

1/ f^{2}

is a hard physical law that always holds

False — it follows only from the approximation

V \propto f

near the operating region; outside that regime (e.g. voltage floored by threshold limits) the relationship breaks.

Two chips with identical benchmark scores are equally valuable

False — if they burn different power (say 100 W vs 50 W), the lower-power one is far more valuable in battery life and cooling cost, which is exactly why perf/watt exists.

Spot the error

P_{dyn} = α C V f

, so power is linear in voltage." — find the flaw

The voltage exponent is wrong; it is

V^{2}

because the energy stored on a gate capacitor is

\frac{1}{2} C V^{2}

, paid each switch — so dynamic power is quadratic in

V

"Since

P = V I

, dropping voltage by 20% drops power by 20%." — what's wrong

That treats power as linear in

V

, but dynamic power's

V^{2}

term dominates switching; and lowering

V

also often lowers achievable

f

, so the drop is steeper than linear.

"Perf/watt

\propto 1/ f^{3}

because power goes as

f^{3}

." — correct the reasoning

Power goes as

f^{3}

but performance goes as

f^{1}

; perf/watt =

f / f^{3} = 1/ f^{2}

, not

1/ f^{3}

— you must divide by performance, not treat it as constant.

"Race-to-idle always saves energy: finish fast, then sleep." — why is this only sometimes true

Racing needs high

f

and high

V

, and

P \propto V^{2} f

; the extra power can outweigh the shorter active time, so total energy may rise. It only wins when idle power is very low and the speed-up is cheap in voltage.

"Static power is

P_{static} = V^{2} I_{leak}

." — fix it

It is

P_{static} = V I_{leak}

, plain

P = V I

for the leakage current; there is no squaring because leakage isn't a per-switch capacitor-charging event.

"Dennard scaling means shrinking transistors keeps power density constant forever." — where does it fail

Dennard scaling assumed voltage could keep shrinking with size, but voltage stopped scaling (leakage and threshold limits), so power density stopped staying constant — the breakdown of Dennard scaling is why perf/watt became a hard wall.

Why questions

Why does the

V^{2}

appear in dynamic power rather than

V^{1}

V^{3}

Because a gate acts as a capacitor and the energy to charge it to

V

\frac{1}{2} C V^{2}

— the quadratic comes straight from capacitor energy storage.

Why did the industry pivot to multicore instead of just raising clock speed

Because perf/watt falls like

1/ f^{2}

as you push a single core's frequency; adding more cores at moderate

f

gains performance far more cheaply in power (see Multicore and Parallelism).

Why is DVFS so effective at saving energy

Lowering

V

cuts dynamic power quadratically while only costing a linear loss in frequency/performance, so efficiency (perf/watt) actually improves as you throttle down.

Why does leakage couple to reliability and thermals, not just to power

Leakage grows exponentially with temperature, so heat causes more leakage which causes more heat — a positive feedback that can lead to thermal runaway if cooling can't keep up (see Leakage Current and Temperature).

Why do the "per second" units cancel in perf/watt

Performance is work-per-second and power is energy-per-second; dividing them cancels the shared per-second, exposing the honest quantity work-per-energy.

Why can raising frequency force a voltage increase

Transistors must fully switch within each shorter clock period; a higher

V

increases drive current so charging happens fast enough, giving the rough relation

f \propto V

near the operating point.

Why isn't TDP the same thing as actual power consumption

TDP is the sustained heat the cooling system is designed to dissipate, a design target — instantaneous power can briefly exceed it (boost) or sit well below it at idle (see Thermal Design Power (TDP)).

Edge cases

What is perf/watt when the chip is fully idle (zero useful operations)

It approaches zero — performance in the numerator is ~0 while static/leakage power keeps the denominator positive, so all consumed energy is "wasted" per the efficiency metric.

If activity factor

α \to 0

, does the chip use zero power

No — dynamic power vanishes but static leakage

V I_{leak}

remains as an always-on drain, so total power bottoms out at the leakage floor, not zero.

At extremely low voltage, why can lowering

V

further hurt efficiency

Below a point

V

can no longer drop without

f

collapsing (transistors barely switch), and the fixed leakage/static power starts dominating, so ops/joule falls — there is an efficiency sweet spot, not a monotone gain.

If two identical cores each run at half the frequency instead of one at full frequency, how does efficiency compare

The two half-speed cores deliver the same throughput at much lower

V

each, so total dynamic power (which scales like

f^{3}

per core when

V

tracks

f

) is far lower — this is the core reason multicore wins on perf/watt.

What happens to perf/watt if temperature rises but the workload stays fixed

It worsens: leakage climbs exponentially with temperature, adding static power to the denominator while performance is unchanged, so operations per joule drops.

In the limit of a workload that's purely memory-bound (compute units mostly idle), why can raw FLOPS mislead you

Peak FLOPS assumes full compute utilization; if the workload can't feed the units, real work-per-joule is low despite a high headline number — always benchmark on representative work (see FLOPS and Benchmarking).

Recall One-line takeaway

Almost every trap here is one of three: (1) forgetting the $V^{2}$ / $f^{3}$ nonlinearity, (2) confusing raw speed with efficiency, or (3) ignoring the leakage/temperature floor that never goes to zero.