Energy efficiency (performance per watt): Question bank

6.4.10 · D5 · Hardware › Power, Thermal & Reliability › Energy efficiency (performance per watt)

Is bank mein in topics ke ideas hain: Dynamic vs Static Power, DVFS - Dynamic Voltage and Frequency Scaling, Dennard Scaling, Thermal Design Power (TDP), Leakage Current and Temperature, Multicore and Parallelism, aur FLOPS and Benchmarking. Yahan har symbol parent note mein define kiya gaya hai: $P$ = power (watts = joules/sec), $V$ = supply voltage, $f$ = clock frequency, $C$ = switching capacitance, $α$ = activity factor, $I_{leak}$ = leakage current.

True or false — justify

A faster chip hamesha ek task kam total energy mein complete karta hai

False — energy = power × time; zyada

f

ke liye zyada

V

chahiye aur

P \propto V^{2} f

, isliye power time se zyada tezi se badh sakti hai, aur runtime kam hone ke bawajood total energy badh jaati hai.

Performance per watt mein aur "operations per joule" mein same information hoti hai

True — performance (work/sec) ka "per second" aur power (energy/sec) ka "per second" cancel ho jaate hain, jo bacha woh hai work/energy = operations/joule.

Supply voltage aadhi karne se dynamic power aadhi ho jaati hai

False — dynamic power hai

α C V^{2} f

, jo

V

mein quadratic hai;

V

aadhi karne par (fixed

f

pe) dynamic power aadhi nahi, quarter ho jaati hai.

Fixed voltage pe clock frequency double karne se sirf dynamic power double hoti hai

True agar $V$ sach mein fixed rahe —

f

linear hai

P_{dyn}

mein. Cube law tab aata hai jab

f

badhane par

V

bhi badhana pade.

Zyada raw FLOPS wala chip automatically zyada energy-efficient hota hai

False — efficiency hai FLOPS ÷ watts; zyada power khaane wala tez chip perf/watt mein kam score kar sakta hai (parent note ka Chip A vs Chip B dekho).

Modern deep-nanometer chips mein leakage (static) power ko safely ignore kiya ja sakta hai

False — chote nodes pe leakage total power ka bada hissa ban jaati hai aur temperature ke saath badhti hai, isliye ise ignore karna thermal aur reliability budget bigaad deta hai.

Perf/watt ka

1/ f^{2}

scale hona ek hard physical law hai jo hamesha hold karta hai

False — yeh sirf us approximation se aata hai jahan

V \propto f

operating region ke paas hota hai; us regime ke bahar (jaise voltage threshold limits se floor ho jaaye) relationship toot jaati hai.

Do chips jinke identical benchmark scores hain, equally valuable hote hain

False — agar woh alag power burn karte hain (maano 100 W vs 50 W), toh kam power wala chip battery life aur cooling cost mein kaafi zyada valuable hai — isliye perf/watt exist karta hai.

Spot the error

P_{dyn} = α C V f

, isliye power voltage mein linear hai." — galti dhundho

Voltage ka exponent galat hai; yeh

V^{2}

hona chahiye kyunki gate capacitor pe store hone wali energy

\frac{1}{2} C V^{2}

hoti hai, jo har switch pe pay hoti hai — isliye dynamic power

V

mein quadratic hai.

"Kyunki

P = V I

, voltage 20% girne se power 20% girti hai." — kya galat hai

Yeh power ko

V

mein linear maanta hai, lekin dynamic power ka

V^{2}

term switching dominate karta hai; aur

V

kam karne se achievable

f

bhi aksar kam hoti hai, isliye drop linear se zyada steep hota hai.

"Perf/watt

\propto 1/ f^{3}

kyunki power

f^{3}

se jaati hai." — reasoning sahi karo

Power

f^{3}

se jaati hai lekin performance

f^{1}

se; perf/watt =

f / f^{3} = 1/ f^{2}

1/ f^{3}

nahi — tumhe performance se divide karna hai, use constant nahi maanna.

"Race-to-idle hamesha energy bachata hai: jaldi khatam karo, phir so jao." — yeh sirf kabhi kabhi kyun sach hota hai

Racing ke liye high

f

aur high

V

chahiye, aur

P \propto V^{2} f

; extra power shorter active time se zyada ho sakti hai, isliye total energy badh sakti hai. Yeh tabhi jeet ta hai jab idle power bahut kam ho aur speed-up voltage mein sasta ho.

"Static power hai

P_{static} = V^{2} I_{leak}

." — theek karo

Yeh

P_{static} = V I_{leak}

hai, leakage current ke liye plain

P = V I

; koi squaring nahi hai kyunki leakage koi per-switch capacitor-charging event nahi hai.

"Dennard scaling ka matlab hai transistors shrink karte rehne se power density hamesha constant rahegi." — yeh kahan fail karta hai

Dennard scaling assume karta tha ki voltage size ke saath shrink hoti rahegi, lekin voltage scaling ruk gayi (leakage aur threshold limits ki wajah se), isliye power density constant rehna band ho gayi — Dennard scaling ka breakdown isliye hi perf/watt ek hard wall ban gayi.

Why questions

Dynamic power mein

V^{1}

V^{3}

ki jagah

V^{2}

kyun aata hai

Kyunki gate ek capacitor ki tarah kaam karta hai aur ise

V

tak charge karne ki energy

\frac{1}{2} C V^{2}

hoti hai — quadratic seedha capacitor energy storage se aata hai.

Industry ne sirf clock speed badhane ki jagah multicore ki taraf pivot kyun kiya

Kyunki ek single core ki frequency push karte waqt perf/watt

1/ f^{2}

ki tarah girta hai; moderate

f

pe zyada cores add karna power mein kaafi saste mein performance deta hai (dekho Multicore and Parallelism).

DVFS energy bachane mein itna effective kyun hai

V

kam karna dynamic power ko quadratically cut karta hai jabki frequency/performance mein sirf linear loss hoti hai, isliye throttle down karne par efficiency (perf/watt) actually improve hoti hai.

Leakage sirf power se nahi, reliability aur thermals se bhi kyun couple karti hai

Leakage temperature ke saath exponentially badhti hai, isliye heat zyada leakage create karti hai jo aur heat create karti hai — yeh ek positive feedback hai jo thermal runaway tak le ja sakta hai agar cooling saath na rahe (dekho Leakage Current and Temperature).

Perf/watt mein "per second" units cancel kyun ho jaate hain

Performance work-per-second hai aur power energy-per-second hai; dono ko divide karne par shared per-second cancel ho jaata hai, aur honest quantity work-per-energy saamne aati hai.

Frequency badhane se voltage increase kyun force ho sakti hai

Transistors ko har chote clock period mein puri tarah switch karna hota hai; zyada

V

drive current badhata hai taaki charging itni tezi se ho sake, jisse operating point ke paas rough relation

f \propto V

milta hai.

TDP aur actual power consumption ek cheez kyun nahi hai

TDP woh sustained heat hai jo cooling system dissipate karne ke liye design ki gayi hai, yeh ek design target hai — instantaneous power briefly ise exceed kar sakti hai (boost) ya idle pe kaafi neeche baith sakti hai (dekho Thermal Design Power (TDP)).

Edge cases

Jab chip fully idle ho (zero useful operations), perf/watt kya hoga

Yeh zero ke paas pahunch jaata hai — numerator mein performance ~0 hai jabki static/leakage power denominator ko positive rakhti hai, isliye saari consumed energy efficiency metric ke hisaab se "waste" hai.

Agar activity factor

α \to 0

, kya chip zero power use karta hai

Nahi — dynamic power khatam ho jaati hai lekin static leakage

V I_{leak}

ek hamesha-on drain ki tarah rehti hai, isliye total power leakage floor pe bottom out hoti hai, zero pe nahi.

Bahut kam voltage pe,

V

aur kam karne se efficiency kyun kharab ho sakti hai

Ek point ke neeche

V

aur nahi gir sakti bina

f

collapse kiye (transistors mushkil se switch karte hain), aur fixed leakage/static power dominate karne lagti hai, isliye ops/joule girta hai — efficiency ka ek sweet spot hota hai, monotone gain nahi hoti.

Agar do identical cores ek full-frequency core ki jagah half frequency pe chalein, efficiency kaise compare hogi

Do half-speed cores same throughput dete hain aur har ek ka

V

bahut kam hota hai, isliye total dynamic power (jo

V

f

track karne par per core

f^{3}

se scale hoti hai) kaafi kam hai — yahi wajah hai ki multicore perf/watt mein jeetta hai.

Agar temperature badhe lekin workload fixed rahe toh perf/watt ka kya hoga

Yeh kharab ho jaata hai: leakage temperature ke saath exponentially badhti hai, static power denominator mein add hoti hai jabki performance unchanged rehti hai, isliye operations per joule girta hai.

Purely memory-bound workload ki limit mein (compute units mostly idle), raw FLOPS mislead kyun kar sakta hai

Peak FLOPS full compute utilization assume karta hai; agar workload units ko feed nahi kar sakta, toh real work-per-joule high headline number ke bawajood kam hoga — hamesha representative work pe benchmark karo (dekho FLOPS and Benchmarking).

Recall Ek-line takeaway

Yahan almost har trap teen mein se ek hai: (1) $V^{2}$ / $f^{3}$ nonlinearity bhool jana, (2) raw speed ko efficiency samajh lena, ya (3) leakage/temperature floor ko ignore karna jo kabhi zero nahi jaata.