Exercises — Energy efficiency (performance per watt)

WHAT: Performance per watt bas performance ko power se divide karna hai. WHY: Definition $\frac{\text{Perf}}{\text{Power}}$ dono numbers ko ek honest score mein fuse kar deti hai. $\frac{40\text{GFLOPS}}{20\text{W}}=2\text{GFLOPS/W}.$ Answer: $2\text{GFLOPS/W}$.

$P_{\text{dyn}}=\alpha C{V}^{2}f.$

• $\alpha$ = activity factor (gates ka fraction jo flip ho raha hai),
• $C$ = switched capacitance,
• $V$ = supply voltage (squared appear hota hai — yeh baad mein matter karega),
• $f$ = clock frequency. Parent se mnemonic: "Alpha Cats Voltage-Squared Frequency."

Operations per joule. Performance hai work-per-second aur power hai energy-per-second; "per second" cancel ho jaata hai: $\frac{\text{work}/\text{s}}{\text{energy}/\text{s}}=\frac{\text{work}}{\text{energy}}=\frac{\text{ops}}{\text{joule}}.$ Toh perf/watt batata hai ki ek fixed energy budget (battery) se kitna total work nikala ja sakta hai.

(a) Pehle performance ko power se divide karo: $\frac{60\times 10^{12}\text{FLOP/s}}{300\text{W}}=2\times 10^{11}\text{FLOP/(s⋅W)}.$ Ab requested GFLOPS/W mein convert karo. Prefix "G" (giga) matlab $10^9$ hai, toh $1\text{GFLOPS/W}=10^9\text{FLOP/(s⋅W)}$. Apna number un units mein express karne ke liye $10^9$ se divide karo: $2\times 10^{11}\text{FLOP/(s⋅W)}=\frac{2\times 10^{11}}{10^9}\text{GFLOPS/W}=200\text{GFLOPS/W}.$ (b) Energy per FLOP ops-per-joule ka reciprocal hai (note karo FLOP/(s·W) = FLOP/J): $\frac{1}{2\times 10^{11}\text{FLOP/J}}=5\times 10^{-12}\text{J}=5\text{pJ/FLOP}.$ WHY reciprocal: ops/joule ko ulta karo to milta hai joules/op — confirm hota hai ki perf/watt ≡ work/energy.

WHAT: Humein sirf relative factors chahiye, toh $P_{\text{dyn}}\propto V^{2}f$ mein ratios daalo. ${\left(\frac{0.9}{1.2}\right)}^2\times \frac{2.25}{3}=(0.75{)}^2\times 0.75=0.5625\times 0.75=0.4218\dots$ Answer: $\approx 0.4219$, yani original dynamic power ka lagbhag $42.2\%$. WHY: $\alpha$ aur $C$ unchanged hain, toh woh ratio mein cancel ho jaate hain — sirf $V^{2}f$ move karta hai.

Yaad karo $I_{\text{leak}}$ symbols ki list se woh always-on trickle current hai. Static power bas woh current hai jo voltage se push hoti hai: $P_{\text{stat}}=V{I}_{\text{leak}}=1.0\times 2=2\text{W}.$ Total $=P_{\text{dyn}}+P_{\text{stat}}=8+2=10\text{W}$. Leakage share $=\frac{2}{10}=20\%$. Isliye "sirf dynamic power matter karti hai" deep-nanometer chips mein galat hai.

A: $120/48=2.5\text{GFLOPS/W}$. B: $200/100=2.0\text{GFLOPS/W}$. Efficiency: A jeet ta hai ($2.5>2.0$) — har joule mein zyada kaam. Speed: B jeetta hai ($200>120$ GFLOPS raw). Same answer nahi hai. Faster ≠ more efficient. Battery/thermal-limited device ke liye A chuno; raw throughput ke liye jahan power free ho, B chuno. Upar ki figure mein, B ka orange (speed) bar taller hai, lekin uska teal (perf/watt) bar A se shorter hai — yaad raho teal bars dono ×50 hain visibility ke liye, toh unki relative height hi message carry karti hai, aur A ka teal genuinely taller hai.

WHY $1/f^2$: performance $\propto f$ hai, lekin $V\propto f$ scaling ke under power $\propto f^3$ hai, toh perf/watt $\propto f/f^3=1/f^2$. $\frac{1}{1.25^2}=\frac{1}{1.5625}=\mathrm{0.64.}$ Perf/watt apni original value ke $64\%$ tak gir jaati hai — sirf $25\%$ speed gain ke liye $36\%$ drop. Woh asymmetry hi wajah hai kyun clock-only scaling khatam hui aur hum multicore ki taraf gaye.

WHAT: Total energy = power × time.

• X: $60\text{W}\times 10\text{s}=600\text{J}$.
• Y: $30\text{W}\times 16\text{s}=480\text{J}$. Y kam energy use karta hai ($480<600\text{J}$), bhale hi slower ho. WHY fast wala haara: X ko higher $V$ aur $f$ chahiye tha; power ($\propto V^{2}f$) time se zyada tezi se badhi. Jaldi khatam karna guarantee nahi karta ki energy bhi kam lagegi.

Naya dynamic: ratio $=(0.8{)}^2\times (1.6/2.0)=0.64\times 0.8=0.512$. $P_{\text{dyn}}^{\prime }=10\times 0.512=5.12\text{W}.$ Naya static: $P_{\text{stat}}=V{I}_{\text{leak}}$ (symbols ki list se fixed leakage current $I_{\text{leak}}$ ke saath), aur $V$ $0.8$ se gira: $P_{\text{stat}}^{\prime }=2\times 0.8=1.6\text{W}.$ Naya total: $5.12+1.6=6.72\text{W}$ (pehle $12\text{W}$ tha). Performance $f$ ko track karta hai: ratio $=1.6/2.0=0.8$. Perf/watt improvement $=\frac{\text{perf ratio}}{\text{power ratio}}=\frac{0.8}{6.72/12}=\frac{0.8}{0.56}=1.4286$. WHY sirf $V^{2}f$ dynamic ke liye move karta hai: $P_{\text{dyn}}=\alpha C{V}^{2}f$. Yahan $\alpha$ (activity) aur $C$ (fixed silicon capacitance) DVFS ke under nahi badte — same gates same transistors par switch karte hain — toh woh "before" aur "after" mein identically appear karte hain aur ratio lete waqt cancel ho jaate hain. Sirf $V$ aur $f$ actually move karte hain, jo $V^{2}f$ chodta hai. WHY static sirf $V$ ke saath scale karta hai: $P_{\text{stat}}=V{I}_{\text{leak}}$, aur $I_{\text{leak}}$ yahan constant rakhe jaane par, static power $V$ mein linear hai — $V$ ka ek factor, squared nahi — toh yeh dynamic se kam aggressively shrink karta hai. Answer: total power $6.72\text{W}$; perf/watt $\approx 42.9\%$ up sirf $20\%$ kam speed ke liye. Note karo leakage pure-dynamic gain ko dilute karta hai (Ex. 2.2 ke $56\%$ se compare karo jahan leakage ignore thi).

Throughput check (cores × frequency): single = $1\times 3\text{GHz}=3.0$; dual = $2\times 1.5\text{GHz}=3.0$. Equal throughput. ✓ WHY $\alpha C$ phir cancel hota hai: har core same silicon design hai, toh $\alpha$ aur $C$ saare cores mein aur dono options mein identical hain — woh comparison se bahar factor out ho jaate hain, har core ki dynamic power $\propto V^{2}f$ chodke. Single-core dynamic ($V=1.0$, $f=3$): $\propto 1.0^2\times 3=3.0$ ($\alpha C\cdot V^{2}f$ ki units mein). Two-core dynamic ($V=0.75$, $f=1.5$, two cores): $2\times (0.75^2\times 1.5)=2\times (0.5625\times 1.5)=2\times 0.84375=\mathrm{1.6875.}$ Ratio $=1.6875/3.0=0.5625$. Answer: same throughput $\approx 56.25\%$ dynamic power par — multicore ki jeet, seedha $V^2$ se. Do slow cores ek fast core ko beat karte hain kyunki har ek lower voltage par run karta hai.

$V$ ke function ke roop mein total power set up karo. $f=2V$ substitute karo: $P(V)=0.5\cdot V^2\cdot (2V)+V\cdot 1.0=V^3+V.$ 5 W par cap: solve karo $V^3+V=5$. Try karo $V=1.5$: $3.375+1.5=4.875$ (thoda under). Try karo $V=1.52$: $3.511+1.52=5.03$. Toh $V\approx 1.5157\text{V}$ — $V_{\text{th}}$ se comfortably above, toh simple model yahan valid hai. $V^{\ast }\approx 1.5157\text{V}\Rightarrow f=2V\approx 3.031\text{GHz}.$ Perf/watt. Performance $\propto f$ hai, aur stated one-op-per-tick assumption se $f=3.031\text{GHz}$ correspond karta hai $3.031\text{GFLOPS}$ se; power cap par $5\text{W}$ hai: $\frac{3.031\text{GFLOPS}}{5\text{W}}\approx 0.606\text{GFLOPS/W}.$ WHY matter karta hai: cube term $V^3$ ceiling ke paas dominate karta hai — last MHz squeeze karna disproportionate power costa hai, exactly isliye phones throttle karte hain. Answer: $f\approx 3.03\text{GHz}$, perf/watt $\approx 0.61\text{GFLOPS/W}$.

WHAT hum optimise kar rahe hain: perf/watt $=\frac{2V}{V^3+V}=\frac{2}{V^2+1}$ (ek $V$ cancel karo). WHY derivative tool: ek smooth function ka maximum dhundhne ke liye hum poochte hain kahan uska slope zero hai — yahi derivative dhundhti hai. $\frac{d}{dV}\left(\frac{2}{V^2+1}\right)=\frac{-2\cdot 2V}{(V^2+1{)}^2}=\frac{-4V}{(V^2+1{)}^2}.$ Yeh $V>0$ ke liye negative hai aur sirf $V=0$ par zero: efficiency $\frac{2}{V^2+1}$ $V$ badhne par monotonically decrease karti hai. Toh is simple model mein theoretical peak sabse kam possible voltage par baithta hai ($V\to 0^{+}$, efficiency $\to 2$). WHY real chips wahan nahi baithte — teen reasons:

1. Frequency mar jaati hai. $f=2V\to 0$, toh chip maximally efficient ban jaati hai lekin har second almost koi kaam nahi karti — woh kabhi deadline meet nahi kar sakti. Efficiency (ops/joule) aur usefulness (ops/second) opposite directions mein pull karte hain.
2. Model $V_{\text{th}}$ ke neeche toot jaata hai. Jab $V$ threshold voltage ke paas jaata hai, transistors subthreshold region mein jaate hain: $f\propto V$ nahi rehta (speed linearly se zyada tezi se collapse hoti hai) aur constant-$I_{\text{leak}}$ assumption fail hoti hai — leakage exponentially badhti hai, toh $P_{\text{stat}}$ per unit work shrink hone ki jagah explode karta hai. Yeh sundar $2/(V^2+1)$ curve wahan simply valid nahi hai.
3. Leakage per second fixed overhead hai. Low $f$ par kaam ko drag out karna chip ko zyada der tak powered rakhta hai, aur $P_{\text{stat}}=V{I}_{\text{leak}}$ har second energy drain karta rehta hai — toh ek point ke baad voltage giraana ek fixed kaam ke liye total energy badha sakta hai. Conclusion: real design target karta hai ==sabse kam voltage jo performance deadline meet kare aur safely $V_{\text{th}}$ se upar rahe== — ek constrained optimum, kabhi mathematical $V\to 0$ peak nahi.

Energy = power × time, nodes par sum karo.

• P: $4\times 250\text{W}\times 2\text{h}=2000\text{Wh}=2.0\text{kWh}$.
• Q: $8\times 150\text{W}\times 1.5\text{h}=1800\text{Wh}=1.8\text{kWh}$. Energy winner: Q ($1.8<2.0\text{kWh}$). Time winner: Q bhi ($1.5\text{h}<2\text{h}$). Yahan Q dono par jeetta hai — low-clock nodes (lower $V$, toh $V^2$ savings) extra nodes ke cost se zyada pay karte hain. Trade-off statement: wide-and-slow (lower voltage par zyada nodes) aksar narrow-and-fast ko energy par beat karta hai, aur yahan time par bhi kyunki 8 nodes kaam ko parallelize karte hain; sirf woh cost jo Q pay karta hai woh hai higher up-front hardware aur zyada total idle/static power (8 chips har ek $V{I}_{\text{leak}}$ leak karte hain jab bhi idle hon), jo reliability aur capital-cost dimension hai jo pure energy sum quietly hide kar deta hai. Toh: is kaam ke liye Q chuno, lekin agar node cost ya leakage-at-idle tumhare budget dominate kare, comparison flip ho sakta hai.