Energy efficiency (performance per watt): Worked examples

6.4.10 · D3 · Hardware › Power, Thermal & Reliability › Energy efficiency (performance per watt)

Shuru karne se pehle, ek reminder un symbols ka jo hum use karte hain (sab parent mein build hue hain — kuch bhi naya assume nahi kiya gaya):

Related builds: Dynamic vs Static Power, DVFS - Dynamic Voltage and Frequency Scaling, Leakage Current and Temperature, Multicore and Parallelism, FLOPS and Benchmarking, Thermal Design Power (TDP), Dennard Scaling.

Scenario matrix

Is topic ka har question inhi cells mein se ek (ya blend) hota hai. Neeche ka har worked example apni cell ke saath tagged hai.

Cell	Situation kya hai	Trap / limiting behaviour
C1	Raw numbers se seedha perf/watt	Units ko ops per joule banana
C2	Do chips compare karo, alag speed aur power	Faster ≠ more efficient
C3	Voltage-only scaling ( $f$ fixed)	Power quadratic hai $V$ mein, linear nahi
C4	Joint $V$ – $f$ scaling (DVFS, $f \propto V$ )	Power $\sim f^{3}$ , perf/watt $\sim 1/ f^{2}$
C5	Dynamic + leakage saath mein	Leakage utni same tarah $V^{2}$ ke saath nahi shrink hoti
C6	Degenerate: zero leakage / leakage-dominated	Kaun sa term vanish hota hai, kaun dominate karta hai
C7	Race-to-idle word problem (total energy, power nahi)	energy = power × time kahin zyada bhi ho sakti hai jab speed up karo
C8	Multicore vs single fast core (exam twist)	Kai slow cores ek hot core se perf/watt mein beat karte hain
C9	Limiting case: $f \to 0$ aur $f \to \infty$	Low $f$ par leakage floor, high $f$ par cube wall

Ab hum har cell hit karte hain.

Figure — Energy efficiency (performance per watt)

Upar ki figure map hai: performance linearly $f$ ke saath badhti hai (yellow), power $f^{3}$ ki tarah badhti hai (red), toh unka ratio — perf/watt (green) — $1/ f^{2}$ ki tarah girta hai. Baar baar iske paas wapas dekho; almost har example in curves par kahin na kahin rehta hai.

C1 — Raw numbers se seedha perf/watt

Worked example Example 1 · Cell C1

Ek CPU $500 GFLOPS$ sustain karta hai jabki $125 W$ draw karta hai. Perf/watt aur energy per FLOP nikalte hain.

Forecast: GFLOPS/W mein perf/watt guess karo aur socho ki energy-per-op picojoule range mein hogi ya nanojoule range mein.

Performance ko power se divide karo. $\frac{500 \times 1 0 ^{9} FLOP/s}{125 W} = 4 \times 1 0^{9} \frac{FLOP}{s\cdotW} = 4 GFLOPS/W .$ Yeh step kyun? Perf/watt literally division hai; kyunki $1 W = 1 J/s$ , upar aur neeche ka "per second" cancel ho jaata hai, FLOP per joule reh jaata hai.
Energy per FLOP ke liye reciprocal lo. $\frac{1}{4 \times 1 0 ^{9} FLOP/J} = 2.5 \times 1 0^{- 10} J/FLOP = 250 pJ/FLOP .$ Yeh step kyun? Ops-per-joule ulta karne se joules-per-op milta hai — ek operation ki asli cost.

Verify: Wapas multiply karo: $4 \times 1 0^{9} FLOP/J \times 2.5 \times 1 0^{- 10} J/FLOP = 1$ ✓ (dimensionless, jaise ek reciprocal pair hona chahiye). Aur $4 GFLOPS/W \times 125 W = 500 GFLOPS$ ✓ original speed recover karta hai.

C2 — Do chips compare karo (faster ≠ better)

C3 — Voltage-only scaling (quadratic trap)

Worked example Example 3 · Cell C3

Ek block $V = 1.2 V$ par chalta hai. Hum $V$ ko $0.6 V$ kar dete hain lekin $f$ fixed rakhte hain (maano $f$ pehle se hi is voltage par comfortable thi). Dynamic power ka kya hoga?

Forecast: Ohm's-law reflex kehta hai "half voltage, half power." Kya yeh sahi hai?

$P_{dyn} = α C V^{2} f$ mein sirf relative factors use karo. $α, C, f$ unchanged hain: $\frac{P _{new}}{P _{old}} = (\frac{V _{new}}{V _{old}})^{2} = (\frac{0.6}{1.2})^{2} = 0.25.$ Yeh step kyun? $V$ ke alaawa sab kuch cancel ho jaata hai, toh ratio purely $V^{2}$ term hai.
Padho. Power 25% tak girta hai — quarter, half nahi. Yeh step kyun? Har gate capacitor par energy $\frac{1}{2} C V^{2}$ hai; $V$ half karne se woh energy quarter ho jaati hai.

Verify: $(0.6)^{2} = 0.36$ , $(1.2)^{2} = 1.44$ , aur $0.36/1.44 = 0.25$ ✓. "Halving power" ka guess 2 ke factor se wrong tha — yahi gap DVFS ka pura payoff hai.

C4 — Joint V–f scaling (cube law)

Worked example Example 4 · Cell C4

DVFS ke under voltage aur frequency saath chalte hain, $f \propto V$ . Hum clock ko $2.0 GHz$ se $3.0 GHz$ tak badhate hain. Dynamic power aur perf/watt mein factor change nikalte hain.

Forecast: 1.5× clock. Power multiplier guess karo — kya woh 1.5 ke paas hai, 2.25 ke paas, ya usse bhi zyada?

Frequency ratio. $\frac{f _{new}}{f _{old}} = \frac{3.0}{2.0} = 1.5.$ Yeh step kyun? Baaki sab factors is ratio se $f \propto V$ ke through pinned hain.
Power $f^{3}$ ki tarah scale hota hai. Kyunki $V \propto f$ , $P_{dyn} \propto V^{2} f = f^{2} \cdot f = f^{3}$ : $\frac{P _{new}}{P _{old}} = 1. 5^{3} = 3.375.$ Yeh step kyun? Clock apne saath voltage bhi upar kheenchta hai, toh voltage se $f^{2}$ aur switching rate se $f$ pay karna padta hai.
Perf/watt $1/ f^{2}$ ki tarah scale hota hai. Performance $\propto f$ , toh $\frac{( Perf/W ) _{new}}{( Perf/W ) _{old}} = \frac{f}{f ^{3}} = \frac{1}{f ^{2}} = \frac{1}{1. 5 ^{2}} = 0.444.$ Yeh step kyun? Perf/watt = perf ÷ power = $f / f^{3}$ .

Verify: Consistency check: perf ratio $= 1.5$ , power ratio $= 3.375$ , toh perf/watt ratio $= 1.5/3.375 = 0.4 \overline{4}$ ✓, $1/1. 5^{2}$ se match karta hai. 50% speed up karne ki cost thi 56% efficiency — exactly woh $1/ f^{2}$ collapse jo map figure ke green curve par dikhta hai.

C5 — Dynamic + leakage saath mein

Worked example Example 5 · Cell C5

Ek core $V = 1.0 V$ par hai, $P_{dyn} = 8 W$ hai aur $I_{leak} = 2 A$ leak karta hai, toh $P_{static} = V I_{leak} = 2 W$ . Hum DVFS apply karte hain: $V \to 0.8 V$ , $f \to 0.8 \times$ (toh $f \propto V$ ), aur (approximately) $I_{leak}$ $2 A$ rehta hai. Naya total power nikalte hain.

Forecast: Dynamic power bahut shrink karega; leakage barely change hogi. Guess karo ki total dynamic-alone ke 51% se zyada girega ya kam.

Naya dynamic power ( $\propto V^{2} f$ , dono 0.8× par girate hain). $P_{dyn,new} = 8 \times (0.8)^{2} \times 0.8 = 8 \times 0.512 = 4.096 W .$ Yeh step kyun? Pehle jaise cube-ish scaling, lekin ab ek real absolute value par apply ki gayi.
Naya static power ( $= V I_{leak}$ , sirf $V$ change hota hai). $P_{static,new} = 0.8 \times 2 = 1.6 W .$ Yeh step kyun? Leakage linearly $V$ ke saath scale hoti hai ( $V I_{leak}$ ke through), quadratically nahi — yeh stubborn hai aur utni jaldi nahi girti.
Jodo. $P_{total,new} = 4.096 + 1.6 = 5.696 W$ (tha $8 + 2 = 10 W$ ). Yeh step kyun? Total power sum hai; dono terms $V$ ke saath alag respond karti hain, toh unhe alag alag scale karna padta hai.

Verify: Total ratio $= 5.696/10 = 0.5696$ . Dynamic-only ratio tha $0.512$ ; kyunki "sticky" leakage sirf $0.8$ tak girti hai, total dynamic-alone (51%) se kam girata hai (57%) ✓ — leakage hamesha DVFS win ko dilute karti hai.

C6 — Degenerate: zero leakage vs leakage-dominated

Worked example Example 6 · Cell C6

Ek $10 W$ chip ke liye do limiting worlds lo aur same $V \to 0.8 \times$ , $f \to 0.8 \times$ move ke liye DVFS outcome predict karo. (a) Ideal old node: saara $10 W$ dynamic hai, leakage $= 0$ . (b) Leaky deep-nanometer node: saara $10 W$ leakage hai, dynamic $\approx 0$ .

Forecast: Kis world mein DVFS zyada help karta hai?

World (a), pure dynamic. $10 \times (0.8)^{2} \times 0.8 = 10 \times 0.512 = 5.12 W$ . Yeh step kyun? Leakage exactly zero hone par $P_{static}$ term vanish ho jaata hai — cube law bina rok ke rule karta hai.
World (b), pure leakage. $10 \times 0.8 = 8.0 W$ . Yeh step kyun? Dynamic $\approx 0$ hone par sirf $V I_{leak}$ bachta hai; yeh linearly $V$ ke saath scale hota hai, toh sirf modest drop.
Compare karo. DVFS world (a) ko 51% tak cut karta hai lekin world (b) ko sirf 80% tak. Yeh step kyun? Degenerate cases har mechanism ko isolate karte hain, dikhate hain ki DVFS ek dynamic-power lever hai — leakage ko barely touch karta hai.

Verify: $0. 8^{3} = 0.512$ ✓ aur $0. 8^{1} = 0.8$ ✓. Yeh mixed Example 5 result $0.5696$ ko bracket karte hain, jo $0.512$ aur $0.8$ ke beech tha ✓ exactly jaise do extremes ka weighted blend hona chahiye.

C7 — Race-to-idle (total energy, power nahi)

Worked example Example 7 · Cell C7

Ek task ko $6 \times 1 0^{12}$ operations chahiye. Do run modes mein se ek choose karo: Fast: $3 GHz$ -equivalent, $3 \times 1 0^{12} ops/s$ sustain karta hai $60 W$ par. Slow: $2 GHz$ -equivalent, $2 \times 1 0^{12} ops/s$ sustain karta hai $24 W$ par. Kaun kam total energy use karke finish karta hai?

Forecast: "Fast pehle finish karta hai, toh pehle idle ho jaata hai aur jeet jaata hai." Sach hai ya trap?

Har mode ke liye time ( $t = work / throughput$ ). $t_{fast} = \frac{6 \times 1 0 ^{12}}{3 \times 1 0 ^{12}} = 2 s, t_{slow} = \frac{6 \times 1 0 ^{12}}{2 \times 1 0 ^{12}} = 3 s .$ Yeh step kyun? Energy power × time hai, toh time chahiye, sirf speed nahi.
Har mode ke liye energy ( $E = P \cdot t$ ). $E_{fast} = 60 \times 2 = 120 J, E_{slow} = 24 \times 3 = 72 J .$ Yeh step kyun? Yeh honest metric hai — fixed kaam khatam karne ke joules.
Compare karo. Slow 72 J use karta hai vs fast ke 120 J → slow 48 J se jeet jaata hai (40% kam energy). Yeh step kyun? Chahe fast 1 s pehle finish kiya, uski power 2.5× zyada thi, aur time sirf 1.5× gira. Power ne fight jeeti.

Verify (perf/watt se): Fast $= 3 \times 1 0^{12} /60 = 5 \times 1 0^{10}$ ops/J; slow $= 2 \times 1 0^{12} /24 = 8.33 \times 1 0^{10}$ ops/J. Energy = work ÷ (ops/J): fast $= 6 \times 1 0^{12} /5 \times 1 0^{10} = 120 J$ ✓, slow $= 6 \times 1 0^{12} /8.33 \times 1 0^{10} = 72 J$ ✓. Dono routes agree karte hain — race-to-idle yahan haar gayi.

C8 — Multicore vs ek hot core (exam twist)

Worked example Example 8 · Cell C8

Tumhe $4 \times 1 0^{12} ops/s$ chahiye. Do tarike hain: Ek hot core: ek single core ko saare $4 \times 1 0^{12} ops/s$ tak push karo; kyunki $f \propto V$ , uski power $f^{3}$ ki tarah scale hoti hai. Ek baseline core $1 \times 1 0^{12} ops/s$ $5 W$ par karta hai. Chaar cool cores: chaar baseline cores har ek $1 \times 1 0^{12} ops/s$ , $5 W$ par, parallel mein chalte hain.

Forecast: Same total throughput — lekin kaun kam power draw karta hai?

Chaar cool cores. Throughput add hoti hai, power add hoti hai: $P_{multi} = 4 \times 5 = 20 W ke liye 4 \times 1 0^{12} ops/s .$ Yeh step kyun? Parallelism speed units add karke efficient point par leti hai, ek unit ko cube par push karke nahi.
Ek hot core $4 \times$ faster hona chahiye, yaani $f \to 4 \times$ , toh $P \propto f^{3}$ : $P_{hot} = 5 \times 4^{3} = 5 \times 64 = 320 W .$ Yeh step kyun? Ek single core $4 \times$ throughput tak pahuncha toh $f^{3}$ wall par chadhta hai — red curve ka punishing region.
Compare karo. $20 W$ vs $320 W$ identical kaam ke liye → multicore 16× zyada efficient hai yahan. Yeh step kyun? Isi liye industry multicore gayi ever-higher clocks chase karne ki bajaye.

Verify: Perf/watt: multi $= 4 \times 1 0^{12} /20 = 2 \times 1 0^{11}$ ops/(s·W); hot $= 4 \times 1 0^{12} /320 = 1.25 \times 1 0^{10}$ . Ratio $= 2 \times 1 0^{11} /1.25 \times 1 0^{10} = 16$ ✓, power ratio $320/20 = 16$ ✓ se match karta hai (throughput equal tha, toh perf/watt ratio = inverse power ratio).

C9 — Limiting cases: $f \to 0$ aur $f \to \infty$

Worked example Example 9 · Cell C9

Ek core ka $P_{static} = 2 W$ (fixed leakage floor) hai aur $P_{dyn} = k f^{3}$ hai jahan $k$ is tarah choose kiya gaya ki $f = 2 GHz$ par dynamic power $8 W$ ho. Clock speed ke dono extremes par perf/watt examine karo (perf $\propto f$ ).

Forecast: Efficiency curve peak kahan karta hai — bahut slow, bahut fast, ya beech mein kahin?

$k$ nikalte hain. $8 = k (2)^{3} = 8 k \Rightarrow k = 1$ ( $f$ GHz mein, power W mein). Yeh step kyun? Constant anchor karne se hum kisi bhi $f$ par evaluate kar sakte hain.
Low-frequency limit $f \to 0$ . $P_{dyn} = f^{3} \to 0$ , toh $P_{total} \to P_{static} = 2 W$ , jabki perf $\propto f \to 0$ . Perf/watt $\propto f / (2 + f^{3}) \to f /2 \to 0$ . Yeh step kyun? Crawl par bhi constant $2 W$ leakage pay karte ho lekin almost koi kaam nahi hota — leakage floor bahut low $f$ par efficiency maar deta hai.
High-frequency limit $f \to \infty$ . $P_{total} \approx f^{3}$ dominate karta hai, perf/watt $\propto f / f^{3} = 1/ f^{2} \to 0$ . Yeh step kyun? Cube wall bahut high $f$ par efficiency maar deta hai.
Toh peak beech mein hai. Efficiency $E (f) = f / (2 + f^{3})$ . Maximise karo: $E^{'} (f) = 0 \Rightarrow (2 + f^{3}) - f (3 f^{2}) = 0 \Rightarrow 2 - 2 f^{3} = 0 \Rightarrow f = 1 GHz$ . Yeh step kyun? Derivative zero karne se pata chalta hai kahan rising work rising power se outpace karna band kar deta hai — woh sweet spot jo parent note ne promise kiya tha.

Verify: $f = 1$ par: $E = 1/ (2 + 1) = 1/3 \approx 0.333$ . $f = 0.5$ par: $E = 0.5/ (2 + 0.125) = 0.235$ . $f = 2$ par: $E = 2/ (2 + 8) = 0.20$ . Dono neighbours $0.333$ se neeche hain ✓ — confirm karta hai ki $f = 1 GHz$ genuine maximum hai, aur dono limits $\to 0$ ✓.

Recall Kaun sa cell kaun sa tha?

C7 (race-to-idle) ko C2 (chip compare) se kya alag karta hai? ::: C7 total work fix karta hai aur energy = power × time mangta hai, toh shorter run bhi zyada cost kar sakta hai; C2 steady-state perf/watt compare karta hai unequal throughputs par. C6 mein, pure-leakage world DVFS ke under barely kyun improve hoti hai? ::: Leakage power $V I_{leak}$ hai — $V$ mein linear — toh $0.8 \times$ voltage sirf $0.8 \times$ power cut deta hai, dynamic ke $0.512 \times$ ke muqable. C9 mein, sabse fast clock sabse efficient kyun nahi hai? ::: perf $\propto f$ lekin power $\propto f^{3}$ (plus leakage floor), toh perf/watt $\propto 1/ f^{2}$ high $f$ par collapse ho jaata hai aur leakage floor low $f$ par maar deta hai — peak beech mein rehta hai.

Active recall

Parent topic par wapas jao.