Thermal throttling mechanisms: Worked examples — Hardware deep dive

Before anything, let us name every symbol used on this page, in plain words, so line one is readable and nothing is borrowed unexplained:

Definition The thermal quantities, in words

$P$ — total power, all heat made per second, in watts (W). Think: brightness of a heater.
$R_{θ}$ — thermal resistance, how badly heat is trapped, in °C per watt (°C/W). Small = great cooler, large = poor cooler.
$T_{a}$ — ambient temperature, the air the cooler dumps heat into (°C).
$T_{j}$ — junction temperature, how hot the silicon itself gets (°C).
$T_{t r i p}$ — the trip point, the temperature at which the chip starts slowing itself (°C).
$C_{θ}$ — thermal capacitance (or thermal mass), how much heat energy the chip+heatsink must absorb to rise 1 °C, in joules per °C (J/°C). Big $C_{θ}$ = slow to heat up.
$τ$ — the time constant $τ = R_{θ} C_{θ}$ , in seconds (s); how long the junction takes to "settle" toward its final temperature.

The scenario matrix

Every problem this topic can pose is one of these cells. Read the "Cell" column — each worked example is tagged with it.

Cell	Case class	The question it asks	Example
A	$T_{j} < T_{t r i p}$ (cool, positive margin)	Does it throttle?	Ex 1
B	$T_{j} > T_{t r i p}$ (hot, negative margin)	By how much must it slow?	Ex 2
C	$T_{j} = T_{t r i p}$ exactly (the boundary)	Max sustainable power	Ex 3
D	Zero / degenerate input ( $P = 0$ , or $R_{θ} = 0$ )	Limiting behaviour	Ex 4
E	$R_{θ} \to \infty$ (no cooler at all)	Other limit	Ex 4
F	Voltage vs frequency lever comparison	Which cut hurts less?	Ex 5
G	Transient / turbo (time constant $τ$ )	Can we boost, and for how long?	Ex 6
H	Real-world word problem (dried paste)	Diagnose from symptoms	Ex 7
I	Exam twist (solve backwards for $R_{θ}$ )	Design the cooler	Ex 8
J	Degenerate ambient ( $T_{a} \geq T_{t r i p}$ )	Cooling impossible	Ex 9

The two workhorse equations:

The picture above is the mental model for every example: power pushes "uphill" through the resistance $R_{θ}$ , raising $T_{j}$ above the ambient floor. Throttling shrinks the source arrow.

The worked examples

Cell A — cool chip, comfortable margin

Cell B — hot chip, negative margin

Worked example Example 2 — How much must it slow? (Cell B)

Same cooler $R_{θ} = 0.6$ , $T_{a} = 25$ , trip $95$ . Now a heavy workload wants $P = 140$ W. Show it exceeds trip, then find the frequency cut (fixed voltage) to fix it. Currently $f = 4.2$ GHz.

Forecast: 140 W is huge. Guess: $T_{j}$ overshoots 95 °C, and we must cut $f$ by roughly the ratio of "allowed power" to "wanted power."

Show it overshoots. $T_{j} = 25 + 140 (0.6) = 25 + 84 = 109$ °C. Since $109 > 95$ → overheating, must throttle. Why? Confirms we are in Cell B (negative margin) before acting.
Find max sustainable power. Solve $95 = 25 + P_{ma x} (0.6) \Rightarrow P_{ma x} = (95 - 25) /0.6 = 116. \overline{6}$ W. Why? The safe boundary is exactly $T_{j} = T_{t r i p}$ ; that power is our budget.
Scale frequency. At fixed $V$ , $P \propto f$ , so $f_{n e w} = f \cdot \frac{P _{ma x}}{P _{n o w}} = 4.2 \cdot \frac{116.667}{140} = 3.5$ GHz. Why? $P_{d y n} = α C V^{2} f$ is linear in $f$ when $V$ is held fixed, so power and frequency scale by the same factor.

Answer: drop to 3.5 GHz.

Verify: At 3.5 GHz power $= 140 \cdot (3.5/4.2) = 116.67$ W, giving $T_{j} = 25 + 116.67 (0.6) = 95.0$ °C — exactly the trip. ✓

Cell C — the boundary, max sustainable power

Cells D & E — degenerate & limiting inputs

Worked example Example 4 — The edge cases (Cells D and E)

Explore three degenerate inputs using $T_{a} = 30$ °C.

Forecast: What happens when the heater is off? When the cooler is perfect? When there is no cooler at all?

$P = 0$ (chip idle / power-gated). $T_{j} = 30 + 0 \cdot R_{θ} = 30$ °C. Why? No heat source → junction sits at ambient. A gated block cannot overheat.
$R_{θ} = 0$ (perfect infinite cooler). $T_{j} = 30 + P \cdot 0 = 30$ °C for any $P$ . Why? Zero resistance means heat escapes with zero temperature rise — the ideal, unreachable limit. No throttling ever.
$R_{θ} \to \infty$ (no cooler — bare die in vacuum). $T_{j} = 30 + P \cdot \infty \to \infty$ . Why? With nowhere for heat to go, temperature runs away — the exact failure throttling exists to prevent. This is why an unplugged fan trips THERMTRIP fast.

Verify: All three follow from $T_{j} = T_{a} + P R_{θ}$ by substituting $0$ , $0$ , and $\infty$ . Units consistent; limits monotonic (more $R_{θ}$ ⇒ hotter). ✓

The straight line above is $T_{j}$ vs $P$ : its slope is $R_{θ}$ and its intercept is $T_{a}$ . Cell D is the intercept; steeper lines (bigger $R_{θ}$ ) hit the trip sooner.

Cell F — voltage vs frequency, which lever?

Worked example Example 5 — DVFS beats pure clock throttling (Cell F)

A core runs at $V = 1.20$ V, $f = 4.0$ GHz, drawing $P_{0} = 150$ W. We must reach $P_{t a r g e t} = 100$ W. Compare two plans.

Forecast: Both plans cut power the same amount — but which one costs less performance? Guess: dropping voltage lets us keep more speed.

Plan A — cut frequency only (fixed $V$ ). $P \propto f$ , so $\frac{f _{A}}{f _{0}} = \frac{P _{t a r g e t}}{P _{0}} = \frac{100}{150} = 0.667$ . New $f_{A} = 4.0 \times 0.667 = 2.667$ GHz. Speed kept: 66.7%. Why? Linear-in- $f$ law; the whole 33% power cut comes from frequency, so 33% of speed is lost.
Plan B — DVFS, drop $V$ to 1.05 V too. Voltage factor: $(1.05/1.20)^{2} = (0.875)^{2} = 0.765625$ . So before touching $f$ , power is already $150 \times 0.765625 = 114.84$ W. Why? Power is quadratic in $V$ ; a modest voltage trim removes a big chunk of heat for free.
Finish Plan B with a small $f$ trim. Need factor $100/114.84 = 0.8708$ more. $f_{B} = 4.0 \times 0.8708 = 3.483$ GHz. Speed kept: 87.1%. Why? Only the remaining gap is paid for in frequency, so far less speed is lost.

Answer: Same 100 W target, but Plan A keeps 2.67 GHz while Plan B keeps 3.48 GHz — DVFS is ~0.82 GHz faster for the identical thermal outcome. See DVFS Dynamic Voltage and Frequency Scaling.

Verify: Plan A: $150 \times (2.667/4.0) = 100.0$ W ✓. Plan B: $150 \times (1.05/1.20)^{2} \times (3.483/4.0) = 150 \times 0.765625 \times 0.8708 = 100.0$ W ✓. Both land on 100 W; Plan B's frequency is higher. ✓

Cell G — transient boost with the time constant

Worked example Example 6 — How long can we boost past sustainable power? (Cell G)

Cooler $R_{θ} = 0.6$ °C/W, ambient $T_{a} = 30$ °C, trip $T_{t r i p} = 82$ °C. Thermal mass $C_{θ} = 13.3$ J/°C, so $τ = R_{θ} C_{θ} = 0.6 \times 13.3 \approx 8$ s. A burst runs at $P_{b oos t} = 90$ W starting from $T_{0} = 60$ °C. The transient law is $T_{j} (t) = T_{\infty} + (T_{0} - T_{\infty}) e^{- t / τ}$ When does throttling kick in?

Forecast: First find the sustainable power from this cooler and trip, confirm 90 W exceeds it, then find how long thermal mass delays the trip.

Derive the sustainable power (so "90 W is a boost" is not just asserted). Set $T_{j} = T_{t r i p}$ : $82 = 30 + P_{s u s t} (0.6) \Rightarrow P_{s u s t} = (82 - 30) /0.6 = 86. \overline{6}$ W. Since $90 > 86.7$ , 90 W truly is above sustainable — hence a boost that must eventually throttle. Why? This ties the "sustainable" claim directly to the given $R_{θ}$ , $T_{a}$ , $T_{t r i p}$ instead of quoting a number from nowhere.
Find the final temperature at 90 W. $T_{\infty} = 30 + 90 (0.6) = 84$ °C. Note $84 > 82$ : left alone, the junction would exceed the trip, so throttling is inevitable. Why? The transient curve climbs toward $T_{\infty}$ ; if $T_{\infty}$ is above the trip, it must cross it.
Set $T_{j} (t) = T_{t r i p}$ . $82 = 84 + (60 - 84) e^{- t /8} = 84 - 24 e^{- t /8}$ . Why? We want the instant the rising curve crosses the trip line.
Isolate the exponential. $24 e^{- t /8} = 84 - 82 = 2 \Rightarrow e^{- t /8} = 2/24 = 0.08333$ . Why? Standard algebra to expose $t$ inside the exponent.
Take the natural log (the tool that undoes $e^{x}$ — that is precisely why we use $ln$ here, and not, say, a square root). $- t /8 = ln (0.08333) = - 2.4849 \Rightarrow t = 8 \times 2.4849 = 19.9$ s. Why? $ln$ is the inverse of the exponential, so it pulls the unknown $t$ out of the exponent.

Answer: the chip can hold 90 W for ≈ 19.9 s before the junction reaches 82 °C and throttling engages. Thermal mass ( $τ = R_{θ} C_{θ}$ ) bought those seconds — exactly why boost/turbo is legal past TDP.

Verify: $T_{j} (19.9) = 84 - 24 e^{- 19.9/8} = 84 - 24 (0.0833) = 84 - 2.0 = 82.0$ °C ✓. At $t = 0$ : $84 - 24 = 60$ °C matches $T_{0}$ ✓. And $P_{s u s t} = 86.7 < 90$ confirms the boost premise. ✓

The rising curve (amber) approaches $T_{\infty} = 84$ °C but only crosses the dashed trip at ~20 s — the flat early slope is the thermal mass "storing" heat before the junction feels it.

Cell H — real-world diagnosis

Worked example Example 7 — The dried-paste mystery (Cell H)

A PC that ran fine at $P = 65$ W and $T_{j} = 62.5$ °C (cooler $R_{θ} = 0.5$ , $T_{a} = 30$ ) now throttles at the same 65 W. Thermal paste has dried out. If $T_{j}$ now measures 92.5 °C at 65 W, what is the new $R_{θ}$ , and what went wrong?

Forecast: Same power, hotter chip ⇒ heat is escaping worse ⇒ $R_{θ}$ must have risen. Guess: it roughly doubled.

Solve the thermal law backwards for $R_{θ}$ . $92.5 = 30 + 65 R_{θ} \Rightarrow R_{θ} = (92.5 - 30) /65 = 62.5/65 = 0.9615$ °C/W. Why? We know $T_{j}$ , $T_{a}$ , $P$ ; the only unknown is the resistance, so rearrange.
Compare to healthy value. Old $0.50 \to$ new $0.96$ °C/W, nearly double. Why? Dried paste is a thin insulating gap; it adds series thermal resistance.

Answer: $R_{θ}$ jumped to ≈ 0.96 °C/W. The chip isn't broken — the cooling path degraded. Fix: re-paste, not replace the CPU.

Verify: With $R_{θ} = 0.9615$ : $T_{j} = 30 + 65 (0.9615) = 30 + 62.5 = 92.5$ °C ✓. Higher $R_{θ}$ ⇒ hotter at same power, as forecast. ✓

Cell I — exam twist: design the cooler

Worked example Example 8 — Backwards design (Cell I)

Exam-style: A 125 W chip must never exceed $T_{j} = 90$ °C in a 40 °C server room. What is the maximum allowable $R_{θ}$ for the heatsink you must specify?

Forecast: Hot room + high power + tight limit ⇒ we need a good (small) cooler. Guess: well under 0.5 °C/W.

Write the constraint at the worst case. $T_{j} = T_{a} + P R_{θ} \leq 90$ , worst case equality: $90 = 40 + 125 R_{θ, ma x}$ . Why? The design margin is tightest exactly at $T_{j} = T_{t r i p}$ ; that gives the largest resistance we can tolerate.
Solve for $R_{θ, ma x}$ . $R_{θ, ma x} = (90 - 40) /125 = 50/125 = 0.40$ °C/W. Why? Any heatsink with $R_{θ} \leq 0.40$ keeps $T_{j}$ at or below 90 °C; anything larger overheats.

Answer: specify a heatsink with $R_{θ} \leq 0.40$ °C/W.

Verify: At $R_{θ} = 0.40$ : $T_{j} = 40 + 125 (0.40) = 40 + 50 = 90$ °C — exactly the limit ✓. A smaller $R_{θ}$ (better cooler) gives lower $T_{j}$ , safe. ✓

Cell J — ambient hotter than the trip point

Worked example Example 9 — Cooling is physically impossible (Cell J)

A chip sits in a sealed enclosure where $T_{a} = 100$ °C, with trip $T_{t r i p} = 95$ °C. The chip draws any $P > 0$ . Can any cooler keep it under the trip?

Forecast: The junction can never be below the air it dumps into. If the air itself is already above the trip, guess: no heatsink on Earth can help.

Read the thermal law at $P > 0$ . $T_{j} = T_{a} + P R_{θ} = 100 + P R_{θ} \geq 100$ °C, since $P R_{θ} \geq 0$ always. Why? $R_{θ}$ can never be negative — heat only flows from hot to cold — so the added term can only raise $T_{j}$ , never lower it below $T_{a}$ .
Compare to trip. $T_{j} \geq 100 > 95 = T_{t r i p}$ for every positive power and every finite cooler. Why? Even the perfect $R_{θ} = 0$ cooler gives $T_{j} = T_{a} = 100 > 95$ .

Answer: the chip throttles perpetually and still cannot cool down — it will drop to the deepest throttle state and may hit THERMTRIP. No heatsink can fix an ambient above the trip; you must cool the room ( $T_{a}$ ) instead. This is the hard floor the whole model imposes: $T_{j}$ is never below $T_{a}$ .

Verify: At the ideal $R_{θ} = 0$ : $T_{j} = 100 + 0 = 100$ °C $> 95$ ✓. Any $R_{θ} > 0$ only makes it hotter. The model is monotonic and bounded below by $T_{a}$ . ✓

Active recall

Recall Cover the answers, test the cells

Which cell asks "max sustainable power," and how do you set it up? ::: Cell C — set $T_{j} = T_{t r i p}$ and solve for $P$ . At fixed voltage, halving power needs what frequency change? ::: Halve the frequency, since $P \propto f$ . Why does DVFS keep more speed than pure clock throttling for the same power cut? ::: Power is quadratic in $V$ , so a small voltage drop removes a lot of heat, leaving a smaller frequency cut needed. What happens to $T_{j}$ when $R_{θ} \to \infty$ ? ::: It runs away to infinity — thermal runaway, the failure throttling prevents. Which mathematical tool extracts $t$ from the transient equation, and why? ::: The natural log $ln$ , because it is the inverse of the exponential and undoes $e^{- t / τ}$ . Same power but suddenly throttling — what physical quantity most likely changed? ::: $R_{θ}$ rose (e.g. dried thermal paste), so the junction gets hotter for the same watts. If ambient $T_{a}$ exceeds the trip point, can a better heatsink save the chip? ::: No — $T_{j}$ is never below $T_{a}$ , so you must cool the room, not the chip. What does $C_{θ}$ mean and what are its units? ::: Thermal capacitance / mass — joules per °C (J/°C); how much heat to raise the chip 1 °C.

Connections

Thermal throttling mechanisms — the parent note these examples deepen.
Thermal Resistance and Heatsinks — the $R_{θ}$ every example turns on.
DVFS Dynamic Voltage and Frequency Scaling — Cell F's winning lever.
TDP Thermal Design Power — Cells C and G define and exceed it.
Dynamic vs Static Power — throttling attacks the dynamic term; $P$ here is total heat.
Clock Gating and Power Gating — the $P = 0$ degenerate case (Cell D).
Reliability and Electromigration — why $T_{j, ma x}$ exists in the first place.
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