Question bank — Thermal throttling mechanisms

Throttling means the chip has failed or is defective. ::: False — throttling is the protection working; the chip deliberately slows to stay under $T_{j,max}$. The real fault to chase is inadequate cooling (high $R_{\theta }$), not the throttling behaviour. Lowering only the clock frequency is just as thermally effective as DVFS. ::: False — frequency enters $P_{dyn}$ linearly, but voltage enters as $V^2$ and speed needs $f\propto V$, so DVFS scales power like $\sim V^3$ and saves far more heat per unit of lost speed. A chip can never draw more than its TDP. ::: False — TDP is a sustained cooling-design target, not a hard cap. Thermal mass ($\tau =R_{\theta }{C}_{\theta }$) lets boost states exceed TDP for seconds until the heatsink warms. Throttling reduces static (leakage) power. ::: Mostly false — DVFS/clock-based throttling directly attacks the dynamic term $\alpha C{V}^{2}f$; leakage is only reduced indirectly because lower voltage and lower temperature both cut leakage. See Dynamic vs Static Power. If a chip is throttling, buying a bigger heatsink can eliminate it. ::: Often true — a lower $R_{\theta }$ means $T_j=T_a+P{R}_{\theta }$ stays below the trip point at the same power, so the chip runs full speed. But it fails to help if the ambient $T_a$ itself is too high. Hysteresis makes the chip run slower on average. ::: False — hysteresis (disengaging at $T_{trip}-\Delta$, not exactly at $T_{trip}$) only prevents rapid on/off chatter; it stabilises switching without meaningfully lowering average performance. Two identical chips at the same power will reach the same junction temperature. ::: False — $T_j=T_a+P{R}_{\theta }$ depends on both ambient $T_a$ and the cooling $R_{\theta }$. Different rooms or coolers give different $T_j$ for the same $P$. Emergency shutdown (THERMTRIP) happens at the same temperature as the throttle trip point. ::: False — the trip point $T_{trip}$ sits below $T_{j,max}$ for margin; THERMTRIP is the last-resort hard power-off at $T_{j,max}$ after gentler mechanisms failed.

"Dynamic power is $P=CVf$, so cutting voltage in half halves the power." ::: Error: the correct law is $P_{dyn}=\alpha C{V}^{2}f$. Voltage is squared, so halving $V$ (at fixed $f$) quarters that factor, not halves it — and in real DVFS $f$ drops too, compounding the saving toward $\sim V^3$. "Since heat flows instantly, the junction temperature jumps the moment power rises." ::: Error: there is thermal capacitance $C_{\theta }$, so $T_j(t)=T_{\infty }+(T_0-T_{\infty })e^{-t/\tau }$ rises gradually with time constant $\tau =R_{\theta }{C}_{\theta }$. That delay is exactly what enables turbo boost. "Clock gating and clock throttling are the same thing." ::: Error: clock gating stops the clock to idle blocks (no work lost); clock throttling/duty-cycling inserts idle cycles into active work (T-states), deliberately slowing a running unit. One saves free power, the other sacrifices performance. "Turbo boost proves TDP is a lie / marketing." ::: Error: boost is physically legitimate — thermal mass absorbs the extra energy for a few seconds before $T_j$ rises. TDP is the steady-state number the cooler must handle; boost is the transient the mass permits. "Because $T_j=T_a+P{R}_{\theta }$ is linear, doubling power always doubles junction temperature." ::: Error: it doubles the rise $P{R}_{\theta }$ above ambient, not the absolute $T_j$. From $30°\text{C}$ ambient, doubling $P{R}_{\theta }$ from 20 °C to 40 °C moves $T_j$ from 50 °C to 70 °C — not a doubling. "Voltage causes electromigration wear, so throttling voltage down damages the chip." ::: Error: high current density and high temperature drive electromigration; lowering voltage reduces both power and temperature, so throttling improves reliability, it doesn't harm it.

Why does throttling drop voltage and frequency together instead of frequency alone? ::: Because a transistor needs enough voltage to switch reliably at a given speed ($f\propto V$ near threshold), so lowering $f$ permits lowering $V$ — and since $P\propto V^3$ overall, taking both knobs down yields the biggest heat cut per lost performance. Why is voltage the "quadratic-in-$V$ is the whole game" lever? ::: Because switching energy is $\frac{1}{2}C{V}^2$ — the field the supply must drive scales with $V$ and the charge moved also scales with $V$, so energy (and thus power) grows as $V^2$ before you even account for $f\propto V$. Why does a thermal sensor sit on-die rather than on the case or heatsink? ::: Because the silicon junction is where damage happens and it heats first; a case or heatsink sensor lags behind $T_j$ by the thermal time constant, reading too cool during a fast spike and reacting too late. Why does throttling exist rather than just letting a chip shut down when hot? ::: Shutdown loses all work; throttling trades a little performance for continued operation, keeping the chip below $T_{j,max}$ while still computing — a slow working chip beats a fast dead one. Why does a better cooler ($R_{\theta }$ lower) let a chip clock higher? ::: A smaller $R_{\theta }$ means less temperature rise per watt ($T_j=T_a+P{R}_{\theta }$), so the junction reaches the trip point at a higher power, letting more of the $P_{dyn}=\alpha C{V}^{2}f$ budget go to a higher $f$. See Thermal Resistance and Heatsinks. Why does hysteresis prevent oscillation but a single sharp trip point does not? ::: With one point, the tiny cooling from throttling immediately re-crosses the trip, re-enabling full power, which re-heats — a fast on/off chatter. A gap $\Delta$ forces the chip to cool meaningfully before releasing, giving clean stable switching.

What happens at $P=0$ (chip idle) — is $T_j$ equal to ambient? ::: In steady state yes: $T_j=T_a+0\cdot R_{\theta }=T_a$. The junction can never be cooler than ambient with passive cooling, because heat only flows from hot to cold. If ambient temperature $T_a$ already exceeds the trip point, what can throttling achieve? ::: Nothing helpful — $T_j=T_a+P{R}_{\theta }\ge T_a>T_{trip}$ even at zero power, so the chip cannot avoid the trip by slowing down; only lowering ambient or improving cooling helps. During a sub-second burst, why can a chip legally exceed sustainable power? ::: Because $T_j$ lags via $\tau =R_{\theta }{C}_{\theta }$; over a time $\ll \tau$ the junction has barely warmed, so the extra energy is temporarily stored in thermal mass rather than raising temperature past the limit. As $t\to \infty$ under constant power, where does $T_j$ settle? ::: The exponential $e^{-t/\tau }$ decays to zero, so $T_j\to T_{\infty }=T_a+P{R}_{\theta }$ — the steady-state value. If that value exceeds the trip point, sustained throttling is unavoidable. If activity factor $\alpha \to 0$ (nothing toggling), what is dynamic power? ::: $P_{dyn}=\alpha C{V}^{2}f\to 0$ — no switching means no dynamic dissipation. This is the limiting case that clock gating exploits: freeze the clock to idle blocks so their $\alpha$ effectively drops to zero. On a multicore chip near the limit, why might the controller park a whole core rather than deepen DVFS on all cores? ::: Parking removes an entire core's leakage and switching at once (a large discrete heat cut), which can be more effective than shaving every core's voltage further when the remaining cores still have thermal headroom to run fast. What is the limiting behaviour if $R_{\theta }\to 0$ (a perfect cooler)? ::: $T_j=T_a+P\cdot 0=T_a$ regardless of power, so the junction never leaves ambient and throttling never triggers — the theoretical ideal that real finite-$R_{\theta }$ heatsinks only approach.