Thermal throttling mechanisms: Worked examples — Hinglish deep dive

6.4.6 · D3 · Hardware › Power, Thermal & Reliability › Thermal throttling mechanisms

Kuch bhi shuru karne se pehle, is page par use hone wale har symbol ko plain words mein naam dete hain, taaki pehli line readable ho aur kuch bhi unexplained na ho:

Definition Thermal quantities, words mein

$P$ — total power, ek second mein bana hua sara heat, watts (W) mein. Socho: ek heater ki brightness.
$R_{θ}$ — thermal resistance, heat kitni buri tarah se trap hota hai, °C per watt (°C/W) mein. Chhota = achha cooler, bada = bekar cooler.
$T_{a}$ — ambient temperature, woh hawa jisme cooler heat dump karta hai (°C).
$T_{j}$ — junction temperature, silicon khud kitna garam hota hai (°C).
$T_{t r i p}$ — trip point, woh temperature jis par chip khud ko slow karna shuru karti hai (°C).
$C_{θ}$ — thermal capacitance (ya thermal mass), chip+heatsink ko 1 °C utha ne ke liye kitna heat energy absorb karna padta hai, joules per °C (J/°C) mein. Bada $C_{θ}$ = dheere garam hona.
$τ$ — time constant $τ = R_{θ} C_{θ}$ , seconds (s) mein; junction ko apne final temperature tak "settle" hone mein kitna waqt lagta hai.

Scenario matrix

Is topic ka har problem inhi cells mein se ek hai. "Cell" column padho — har worked example iske saath tagged hai.

Cell	Case class	Yeh kya poochta hai	Example
A	$T_{j} < T_{t r i p}$ (cool, positive margin)	Kya yeh throttle karta hai?	Ex 1
B	$T_{j} > T_{t r i p}$ (hot, negative margin)	Ise kitna slow karna padega?	Ex 2
C	$T_{j} = T_{t r i p}$ exactly (boundary)	Max sustainable power	Ex 3
D	Zero / degenerate input ( $P = 0$ , ya $R_{θ} = 0$ )	Limiting behaviour	Ex 4
E	$R_{θ} \to \infty$ (bilkul bhi cooler nahi)	Doosri limit	Ex 4
F	Voltage vs frequency lever comparison	Kaun sa cut kam hurt karta hai?	Ex 5
G	Transient / turbo (time constant $τ$ )	Kya hum boost kar sakte hain, aur kitni der tak?	Ex 6
H	Real-world word problem (dried paste)	Symptoms se diagnose karo	Ex 7
I	Exam twist ( $R_{θ}$ ke liye backwards solve karo)	Cooler design karo	Ex 8
J	Degenerate ambient ( $T_{a} \geq T_{t r i p}$ )	Cooling impossible	Ex 9

Do workhorse equations:

Upar ki picture har example ke liye mental model hai: power "uphill" push karta hai resistance $R_{θ}$ ke through, $T_{j}$ ko ambient floor se upar uthata hai. Throttling source arrow ko chhota karta hai.

Worked examples

Cell A — cool chip, comfortable margin

Worked example Example 1 — Kya yeh throttle karta hai? (Cell A)

Ek laptop CPU $P = 45$ W dissipate karta hai. Cooler: $R_{θ} = 0.6$ °C/W. Ambient $T_{a} = 25$ °C. Trip $T_{t r i p} = 95$ °C. Throttle hoga ya nahi?

Forecast: Computing se pehle guess karo — 45 W modest hai aur cooler decent hai. Kya $T_{j}$ 95 °C se kaafi neeche rahega?

$T_{j}$ compute karo. $T_{j} = T_{a} + P R_{θ} = 25 + 45 (0.6) = 25 + 27 = 52$ °C. Yeh step kyun? Steady-state law directly ek power ko junction temperature mein convert karta hai — sensor bas yahi number care karta hai.
Trip se compare karo. $52 < 95$ , margin $= 95 - 52 = 43$ °C. Yeh step kyun? Throttling ek comparison hai; margin ka sirf sign decide karta hai.

Answer: throttling nahi, 43 °C ka headroom hai.

Verify: Units: $[W] \cdot [°C/W] = °C$ ✓. Sanity: trip temperature ka adha se bhi kam — clearly safe.

Cell B — hot chip, negative margin

Worked example Example 2 — Ise kitna slow karna padega? (Cell B)

Wahi cooler $R_{θ} = 0.6$ , $T_{a} = 25$ , trip $95$ . Ab ek heavy workload $P = 140$ W chahta hai. Dikhao ki yeh trip exceed karta hai, phir use fix karne ke liye frequency cut nikalo (fixed voltage). Abhi $f = 4.2$ GHz hai.

Forecast: 140 W bahut zyada hai. Guess: $T_{j}$ 95 °C se overshoot karega, aur hume $f$ ko roughly "allowed power" se "wanted power" ke ratio se cut karna hoga.

Dikhao ki overshoot hota hai. $T_{j} = 25 + 140 (0.6) = 25 + 84 = 109$ °C. Kyunki $109 > 95$ → overheating, throttle karna padega. Kyun? Confirm karta hai ki act karne se pehle hum Cell B mein hain (negative margin).
Max sustainable power nikalo. Solve karo $95 = 25 + P_{ma x} (0.6) \Rightarrow P_{ma x} = (95 - 25) /0.6 = 116. \overline{6}$ W. Kyun? Safe boundary exactly $T_{j} = T_{t r i p}$ hai; woh power hamara budget hai.
Frequency scale karo. Fixed $V$ par, $P \propto f$ , toh $f_{n e w} = f \cdot \frac{P _{ma x}}{P _{n o w}} = 4.2 \cdot \frac{116.667}{140} = 3.5$ GHz. Kyun? $P_{d y n} = α C V^{2} f$ jab $V$ fixed ho toh $f$ mein linear hai, isliye power aur frequency same factor se scale hote hain.

Answer: 3.5 GHz par drop karo.

Verify: 3.5 GHz par power $= 140 \cdot (3.5/4.2) = 116.67$ W, giving $T_{j} = 25 + 116.67 (0.6) = 95.0$ °C — exactly trip par. ✓

Cell C — boundary, max sustainable power

Cells D & E — degenerate & limiting inputs

Worked example Example 4 — Edge cases (Cells D aur E)

$T_{a} = 30$ °C use karke teen degenerate inputs explore karo.

Forecast: Kya hota hai jab heater off ho? Jab cooler perfect ho? Jab bilkul cooler na ho?

$P = 0$ (chip idle / power-gated). $T_{j} = 30 + 0 \cdot R_{θ} = 30$ °C. Kyun? Koi heat source nahi → junction ambient par baith jaata hai. Ek gated block overheat nahi ho sakta.
$R_{θ} = 0$ (perfect infinite cooler). $T_{j} = 30 + P \cdot 0 = 30$ °C kisi bhi $P$ ke liye. Kyun? Zero resistance matlab heat bina kisi temperature rise ke escape ho jaati hai — ideal, unreachable limit. Kabhi throttling nahi.
$R_{θ} \to \infty$ (koi cooler nahi — bare die in vacuum). $T_{j} = 30 + P \cdot \infty \to \infty$ . Kyun? Heat ke jaane ki jagah nahi, toh temperature runaway ho jaata hai — exactly woh failure jo throttling prevent karne ke liye exist karta hai. Isliye unplugged fan THERMTRIP jaldi trip karta hai.

Verify: Teenon $T_{j} = T_{a} + P R_{θ}$ mein $0$ , $0$ , aur $\infty$ substitute karke nikle hain. Units consistent; limits monotonic (zyada $R_{θ}$ ⇒ zyada garam). ✓

Upar ki straight line $T_{j}$ vs $P$ hai: iska slope $R_{θ}$ hai aur intercept $T_{a}$ hai. Cell D intercept hai; steeper lines (bada $R_{θ}$ ) trip ko jaldi hit karte hain.

Cell F — voltage vs frequency, kaun sa lever?

Worked example Example 5 — DVFS pure clock throttling se better hai (Cell F)

Ek core $V = 1.20$ V, $f = 4.0$ GHz par run karta hai, $P_{0} = 150$ W draw karta hai. Hume $P_{t a r g e t} = 100$ W reach karna hai. Do plans compare karo.

Forecast: Dono plans same amount power cut karte hain — lekin kaun sa kam performance cost karta hai? Guess: voltage drop karne se zyada speed rakh sakte hain.

Plan A — sirf frequency cut karo (fixed $V$ ). $P \propto f$ , toh $\frac{f _{A}}{f _{0}} = \frac{P _{t a r g e t}}{P _{0}} = \frac{100}{150} = 0.667$ . Naya $f_{A} = 4.0 \times 0.667 = 2.667$ GHz. Speed rakha: 66.7%. Kyun? Linear-in- $f$ law; poora 33% power cut frequency se aata hai, isliye 33% speed kho jaati hai.
Plan B — DVFS, $V$ bhi 1.05 V par drop karo. Voltage factor: $(1.05/1.20)^{2} = (0.875)^{2} = 0.765625$ . Toh $f$ touch karne se pehle, power already $150 \times 0.765625 = 114.84$ W hai. Kyun? Power $V$ mein quadratic hai; ek modest voltage trim bina kuch kiye heat ka bada chunk remove kar deta hai.
Plan B ko chhoti $f$ trim se khatam karo. $100/114.84 = 0.8708$ ka factor aur chahiye. $f_{B} = 4.0 \times 0.8708 = 3.483$ GHz. Speed rakha: 87.1%. Kyun? Sirf remaining gap frequency mein pay kiya jaata hai, isliye bahut kam speed khoyi jaati hai.

Answer: Same 100 W target, lekin Plan A 2.67 GHz rakhta hai jabki Plan B 3.48 GHz rakhta hai — DVFS identical thermal outcome ke liye ~0.82 GHz faster hai. Dekho DVFS Dynamic Voltage and Frequency Scaling.

Verify: Plan A: $150 \times (2.667/4.0) = 100.0$ W ✓. Plan B: $150 \times (1.05/1.20)^{2} \times (3.483/4.0) = 150 \times 0.765625 \times 0.8708 = 100.0$ W ✓. Dono 100 W par land karte hain; Plan B ki frequency zyada hai. ✓

Cell G — transient boost with the time constant

Worked example Example 6 — Sustainable power se zyada kitni der boost kar sakte hain? (Cell G)

Cooler $R_{θ} = 0.6$ °C/W, ambient $T_{a} = 30$ °C, trip $T_{t r i p} = 82$ °C. Thermal mass $C_{θ} = 13.3$ J/°C, toh $τ = R_{θ} C_{θ} = 0.6 \times 13.3 \approx 8$ s. Ek burst $P_{b oos t} = 90$ W par $T_{0} = 60$ °C se shuru hota hai. Transient law hai: $T_{j} (t) = T_{\infty} + (T_{0} - T_{\infty}) e^{- t / τ}$ Throttling kab engage hogi?

Forecast: Pehle is cooler aur trip se sustainable power nikalo, confirm karo ki 90 W use exceed karta hai, phir nikalo ki thermal mass trip ko kitna delay karta hai.

Sustainable power derive karo (taaki "90 W ek boost hai" sirf assert na ho). $T_{j} = T_{t r i p}$ set karo: $82 = 30 + P_{s u s t} (0.6) \Rightarrow P_{s u s t} = (82 - 30) /0.6 = 86. \overline{6}$ W. Kyunki $90 > 86.7$ , 90 W truly sustainable se upar hai — isliye yeh ek boost hai jo eventually throttle karega. Kyun? Yeh "sustainable" claim ko diye gaye $R_{θ}$ , $T_{a}$ , $T_{t r i p}$ se directly tie karta hai kisi number ko nowhere se quote karne ke bajay.
90 W par final temperature nikalo. $T_{\infty} = 30 + 90 (0.6) = 84$ °C. Note karo $84 > 82$ : agar chhod diya, toh junction trip exceed kar deta, isliye throttling inevitable hai. Kyun? Transient curve $T_{\infty}$ ki taraf climb karti hai; agar $T_{\infty}$ trip se upar hai, toh use cross karna hi padega.
$T_{j} (t) = T_{t r i p}$ set karo. $82 = 84 + (60 - 84) e^{- t /8} = 84 - 24 e^{- t /8}$ . Kyun? Hum woh instant chahte hain jab rising curve trip line cross kare.
Exponential isolate karo. $24 e^{- t /8} = 84 - 82 = 2 \Rightarrow e^{- t /8} = 2/24 = 0.08333$ . Kyun? Standard algebra $e^{x}$ ke andar $t$ ko expose karne ke liye.
Natural log lo (woh tool jo $e^{x}$ ko undo karta hai — exactly isliye hum $ln$ use karte hain, koi square root nahi). $- t /8 = ln (0.08333) = - 2.4849 \Rightarrow t = 8 \times 2.4849 = 19.9$ s. Kyun? $ln$ exponential ka inverse hai, isliye yeh unknown $t$ ko exponent se bahar khींch leta hai.

Answer: chip 90 W ko ≈ 19.9 s tak hold kar sakta hai junction ke 82 °C tak pahunchne se pehle aur throttling engage hone se pehle. Thermal mass ( $τ = R_{θ} C_{θ}$ ) ne woh seconds buy kiye — exactly isliye TDP ke baad bhi boost/turbo legal hai.

Verify: $T_{j} (19.9) = 84 - 24 e^{- 19.9/8} = 84 - 24 (0.0833) = 84 - 2.0 = 82.0$ °C ✓. $t = 0$ par: $84 - 24 = 60$ °C $T_{0}$ se match karta hai ✓. Aur $P_{s u s t} = 86.7 < 90$ boost premise confirm karta hai. ✓

Rising curve (amber) $T_{\infty} = 84$ °C ki taraf approach karti hai lekin dashed trip ko sirf ~20 s par cross karti hai — flat early slope thermal mass ka "storing" heat hai junction feel karne se pehle.

Cell H — real-world diagnosis

Worked example Example 7 — Dried-paste mystery (Cell H)

Ek PC jo $P = 65$ W aur $T_{j} = 62.5$ °C par theek run karta tha (cooler $R_{θ} = 0.5$ , $T_{a} = 30$ ) ab same 65 W par throttle karta hai. Thermal paste sukh gayi hai. Agar $T_{j}$ ab 65 W par 92.5 °C measure hoti hai, toh naya $R_{θ}$ kya hai, aur kya galat hua?

Forecast: Same power, hotter chip ⇒ heat zyada buri tarah escape ho rahi hai ⇒ $R_{θ}$ badh gayi hogi. Guess: roughly double ho gayi.

Thermal law ko $R_{θ}$ ke liye backwards solve karo. $92.5 = 30 + 65 R_{θ} \Rightarrow R_{θ} = (92.5 - 30) /65 = 62.5/65 = 0.9615$ °C/W. Kyun? Hume $T_{j}$ , $T_{a}$ , $P$ pata hai; sirf resistance unknown hai, toh rearrange karo.
Healthy value se compare karo. Pehle $0.50 \to$ ab $0.96$ °C/W, lagbhag double. Kyun? Sukhi paste ek thin insulating gap hai; yeh series thermal resistance add karta hai.

Answer: $R_{θ}$ ≈ 0.96 °C/W tak jump ho gayi. Chip toot nahi hai — cooling path degrade ho gaya. Fix: re-paste karo, CPU replace mat karo.

Verify: $R_{θ} = 0.9615$ ke saath: $T_{j} = 30 + 65 (0.9615) = 30 + 62.5 = 92.5$ °C ✓. Zyada $R_{θ}$ ⇒ same power par zyada garam, jaise forecast kiya tha. ✓

Cell I — exam twist: cooler design karo

Worked example Example 8 — Backwards design (Cell I)

Exam-style: Ek 125 W chip ko 40 °C server room mein $T_{j} = 90$ °C se kabhi zyada nahi hona chahiye. Heatsink ke liye specify karne ke liye maximum allowable $R_{θ}$ kya hai?

Forecast: Hot room + high power + tight limit ⇒ hume ek achha (chhota) cooler chahiye. Guess: 0.5 °C/W se kaafi neeche.

Worst case mein constraint likho. $T_{j} = T_{a} + P R_{θ} \leq 90$ , worst case equality: $90 = 40 + 125 R_{θ, ma x}$ . Kyun? Design margin exactly $T_{j} = T_{t r i p}$ par tightest hai; woh maximum resistance deta hai jo hum tolerate kar sakte hain.
$R_{θ, ma x}$ solve karo. $R_{θ, ma x} = (90 - 40) /125 = 50/125 = 0.40$ °C/W. Kyun? Koi bhi heatsink $R_{θ} \leq 0.40$ ke saath $T_{j}$ ko 90 °C par ya neeche rakhta hai; kuch bhi bada overheat karta hai.

Answer: $R_{θ} \leq 0.40$ °C/W wala heatsink specify karo.

Verify: $R_{θ} = 0.40$ par: $T_{j} = 40 + 125 (0.40) = 40 + 50 = 90$ °C — exactly limit par ✓. Chhota $R_{θ}$ (better cooler) lower $T_{j}$ deta hai, safe. ✓

Cell J — ambient trip point se zyada garam

Worked example Example 9 — Cooling physically impossible hai (Cell J)

Ek chip ek sealed enclosure mein hai jahan $T_{a} = 100$ °C hai, trip $T_{t r i p} = 95$ °C ke saath. Chip koi bhi $P > 0$ draw karta hai. Kya koi cooler ise trip se neeche rakh sakta hai?

Forecast: Junction kabhi bhi us hawa se neeche nahi ho sakta jisme woh heat dump karta hai. Agar hawa khud hi trip se upar hai, guess: koi bhi heatsink kaam nahi karega.

$P > 0$ par thermal law padho. $T_{j} = T_{a} + P R_{θ} = 100 + P R_{θ} \geq 100$ °C, kyunki $P R_{θ} \geq 0$ hamesha. Kyun? $R_{θ}$ kabhi negative nahi ho sakta — heat sirf hot se cold ki taraf flow karta hai — toh added term sirf $T_{j}$ raise kar sakta hai, kabhi $T_{a}$ se neeche nahi la sakta.
Trip se compare karo. $T_{j} \geq 100 > 95 = T_{t r i p}$ har positive power aur har finite cooler ke liye. Kyun? Perfect $R_{θ} = 0$ cooler bhi $T_{j} = T_{a} = 100 > 95$ deta hai.

Answer: chip hamesha throttle karta rahega aur phir bhi cool down nahi ho sakta — yeh deepest throttle state mein drop karega aur THERMTRIP hit kar sakta hai. Koi bhi heatsink ambient ko trip se upar fix nahi kar sakta; iske bajay tume room ( $T_{a}$ ) cool karna hoga. Yeh hard floor hai jo poora model impose karta hai: $T_{j}$ kabhi bhi $T_{a}$ se neeche nahi hota.

Verify: Ideal $R_{θ} = 0$ par: $T_{j} = 100 + 0 = 100$ °C $> 95$ ✓. Koi bhi $R_{θ} > 0$ ise aur garam hi karta hai. Model monotonic hai aur $T_{a}$ se neeche bounded hai. ✓

Active recall

Recall Answers cover karo, cells test karo

Kaun sa cell "max sustainable power" poochta hai, aur tum ise kaise set up karte ho? ::: Cell C — $T_{j} = T_{t r i p}$ set karo aur $P$ ke liye solve karo. Fixed voltage par, power half karne ke liye frequency mein kya change chahiye? ::: Frequency half karo, kyunki $P \propto f$ . DVFS same power cut ke liye pure clock throttling se zyada speed kyun rakhta hai? ::: Power $V$ mein quadratic hai, toh voltage mein chhoti drop bahut saari heat remove kar deti hai, jisse zyada chhoti frequency cut ki zaroorat padti hai. Jab $R_{θ} \to \infty$ ho toh $T_{j}$ ka kya hota hai? ::: Yeh infinity tak run away karta hai — thermal runaway, woh failure jo throttling prevent karta hai. Transient equation se $t$ extract karne ka kaun sa mathematical tool hai, aur kyun? ::: Natural log $ln$ , kyunki yeh exponential ka inverse hai aur $e^{- t / τ}$ ko undo karta hai. Same power lekin achanak throttling — sabse zyada sambhaavit kya physical quantity change hui? ::: $R_{θ}$ badh gayi (jaise sukhi thermal paste), toh junction same watts par zyada garam ho jaata hai. Agar ambient $T_{a}$ trip point se zyada ho, toh kya better heatsink chip ko bacha sakta hai? ::: Nahi — $T_{j}$ kabhi $T_{a}$ se neeche nahi hota, isliye room cool karna padega, chip nahi. $C_{θ}$ ka kya matlab hai aur iske units kya hain? ::: Thermal capacitance / mass — joules per °C (J/°C); chip ko 1 °C raise karne ke liye kitni heat chahiye.

Connections

Thermal throttling mechanisms — parent note jise yeh examples deepen karte hain.
Thermal Resistance and Heatsinks — $R_{θ}$ jis par har example depend karta hai.
DVFS Dynamic Voltage and Frequency Scaling — Cell F ka winning lever.
TDP Thermal Design Power — Cells C aur G ise define aur exceed karte hain.
Dynamic vs Static Power — throttling dynamic term par attack karta hai; $P$ yahan total heat hai.
Clock Gating and Power Gating — $P = 0$ degenerate case (Cell D).
Reliability and Electromigration — isliye $T_{j, ma x}$ pehle se exist karta hai.
🇮🇳 Hinglish version