Dynamic vs static power consumption: Worked examples

This page is a drill through every case the dynamic/static power formulas can throw at you. We start from the parent page's two master formulas and never assume a step. If a symbol appears, it was defined either here or in 6.4.1 Dynamic vs static power consumption first.

Recall The formulas we will use everywhere

Dynamic power = the two switching-related terms added together: $P_{dynamic} = P_{switching} α C V_{dd}^{2} f + short-circuit P_{sc}$ On most cases the short-circuit term $P_{sc}$ is small, so we often use $P_{dynamic} \approx P_{switching} = α C V_{dd}^{2} f$ ; Cell E handles $P_{sc}$ explicitly. Static (leakage) power: $P_{static} = V_{dd} I_{leak}$ Total: $P_{total} = P_{dynamic} + P_{static}$ .

Meanings (plain words):

$α$ ::: activity factor — fraction of clock ticks on which a node actually flips, between 0 and 1
$C$ ::: load capacitance in farads — how much charge a node must move to change voltage
$V_{dd}$ ::: supply voltage in volts — the "height" the charge is pumped to
$f$ ::: clock frequency in hertz — flips per second
$I_{leak}$ ::: leakage current in amps — the trickle through "off" transistors
$P_{sc}$ ::: short-circuit (shoot-through) power — energy burned when both transistors briefly conduct at once

The scenario matrix

Every power question is one (or a blend) of these case classes. Below, each class gets at least one fully worked example, tagged with its cell letter.

Cell	Case class	What breaks / what to watch
A	Plain plug-in (all values given, non-zero)	unit prefixes pico/giga/milli must cancel cleanly
B	Voltage scaling of dynamic power (ratio question)	$V^{2}$ dominance — never scale linearly
C	Frequency scaling	linear in $f$ — but real DVFS ties $f$ to $V$
D	Activity factor extremes ( $α = 0$ and $α = 1$ )	$α = 0$ ⇒ dynamic vanishes, only leakage left
E	Short-circuit term & the $V_{dd} < 2 V_{t h}$ cutoff	term goes to zero, not negative
F	Static vs dynamic crossover (idle chip)	which term wins at low activity?
G	Real-world word problem (battery / TDP)	translate watts → joules → hours; both terms scale
H	Static power's linear voltage scaling	$P_{static} \propto V_{dd}$ , not $V_{dd}^{2}$
I	Exam twist (combined scaling + solve-for-unknown)	change two variables at once, or invert the formula

The figure below is the map for the whole page: nine coloured tiles, one per case class A–I. As you work each example, find its letter on the tile — the tile colours are reused in the worded steps (lavender = a voltage lever, coral = a ratio/scaling lever, mint = frequency or word-problem, butter = activity or leakage) so you can see at a glance which lever that case pulls. Notice the caption formula at the bottom: every tile is just a way of stressing one piece of $P_{total} = α C V_{dd}^{2} f + V_{dd} I_{leak}$ .

Figure — Dynamic vs static power consumption

Cell A — Plain plug-in

Worked example A1: Single gate switching power

A logic gate has $C = 5$ pF, $V_{dd} = 1.0$ V, $f = 2$ GHz, $α = 0.25$ . Find $P_{switching}$ .

Forecast: guess the order of magnitude first — is this microwatts or watts?

This example lives on the lavender A tile — the plain plug-in that pulls no scaling lever.

Write the formula. $P = α C V_{dd}^{2} f$ . Why this step? We are asked for switching power with all four inputs given, so this is the master formula, no correction needed.
Convert prefixes. $C = 5 \times 1 0^{- 12}$ F, $f = 2 \times 1 0^{9}$ Hz. Why this step? Pico ( $1 0^{- 12}$ ) and giga ( $1 0^{9}$ ) must be in base units so the answer lands in watts.
Multiply. $P = 0.25 \times 5 \times 1 0^{- 12} \times (1.0)^{2} \times 2 \times 1 0^{9}$ $= 0.25 \times 5 \times 2 \times 1 0^{- 12 + 9} = 2.5 \times 1 0^{- 3} W = 2.5 mW$ Why this step? Group the numbers and the powers of ten separately: $1 0^{- 12} \cdot 1 0^{9} = 1 0^{- 3}$ = milli.

Verify: Units: $F \cdot V^{2} \cdot Hz = (C/V) \cdot V^{2} \cdot (1/ s) = C \cdot V / s = J/s = W$ ✓. Order-of-magnitude guess of "milliwatts" was right.

Cell B — Voltage scaling of dynamic power

Worked example B1: Drop the voltage, watch power fall

A block burns $P_{1} = 4.0$ W of switching power at $V_{1} = 1.0$ V. We lower it to $V_{2} = 0.8$ V, keeping $C$ , $f$ , $α$ fixed. New power?

Forecast: a 20% voltage cut — do you expect a 20% power cut, or more?

This is the coral B tile — a ratio question pulling the voltage lever.

Form the ratio. Only $V_{dd}$ changes, so $\frac{P _{2}}{P _{1}} = (\frac{V _{2}}{V _{1}})^{2} .$ Why this step? $C, f, α$ cancel because they are identical in both cases — the ratio isolates the voltage effect.
Compute. $(\frac{0.8}{1.0})^{2} = 0.64$ . Why this step? Power is quadratic in voltage — this is the whole reason Dynamic Voltage Frequency Scaling (DVFS) works.
Scale. $P_{2} = 0.64 \times 4.0 = 2.56$ W. Why this step? The ratio only gave us the fraction of the original power; multiplying by $P_{1}$ converts that fraction back into an absolute number in watts.

Verify: A 20% voltage cut gave a $1 - 0.64 = 36%$ power cut — bigger than 20%, as the quadratic predicts. Sanity: $P_{2} < P_{1}$ ✓. (Contrast this with Cell H, where static power falls only linearly.)

Cell C — Frequency scaling

Worked example C1: Overclocking cost

At $f_{1} = 3$ GHz a core uses $P_{1} = 15$ W switching power. It is overclocked to $f_{2} = 4$ GHz with voltage unchanged. New power?

Forecast: power is linear in $f$ — guess before computing.

This is the mint C tile — the frequency lever, pulled alone.

Ratio. $\frac{P _{2}}{P _{1}} = \frac{f _{2}}{f _{1}}$ since only $f$ changes. Why this step? $f$ appears to the first power, so its ratio scales power directly.
Compute. $\frac{4}{3} \approx 1.333$ . Why this step? We evaluate the ratio numerically so the next step is a plain multiplication; the result exceeding 1 already tells us power will rise.
Scale. $P_{2} = 1.333 \times 15 = 20$ W. Why this step? Multiplying the ratio by the known $P_{1}$ turns the relative change back into absolute watts.

Verify: $\frac{4}{3} \times 15 = 20$ exactly ✓. Note the trap: real overclocking usually raises $V_{dd}$ too, so actual power grows faster than linearly (see Cell I).

Cell D — Activity factor extremes

Worked example D1:

$α = 0$ and $α = 1$ A node has $C = 8$ pF, $V_{dd} = 1.2$ V, $f = 1$ GHz. Also its leakage is $I_{leak} = 2$ nA. Find total power when (i) $α = 0$ (idle, never flips) and (ii) $α = 1$ (flips every cycle).

Forecast: when $α = 0$ , is the power exactly zero?

This is the butter D tile — the activity lever pushed to both extremes.

Switching at $α = 0$ . $P_{sw} = 0 \times C V_{dd}^{2} f = 0$ W. Why this step? No flips ⇒ no charge moved ⇒ no switching energy. This is the degenerate input.
But leakage never sleeps. $P_{static} = V_{dd} I_{leak} = 1.2 \times 2 \times 1 0^{- 9} = 2.4 \times 1 0^{- 9}$ W $= 2.4$ nW. Why this step? Static power does not depend on $α$ — even a frozen circuit leaks.
Total at $α = 0$ : $0 + 2.4 nW = 2.4$ nW. Why this step? Total power is the sum of the dynamic and static terms; with dynamic zeroed, the whole idle draw is pure leakage — the headline lesson of this cell.
Switching at $α = 1$ . $P_{sw} = 1 \times 8 \times 1 0^{- 12} \times (1.2)^{2} \times 1 \times 1 0^{9} = 8 \times 1.44 \times 1 0^{- 3} = 1.152 \times 1 0^{- 2} W .$ That is $11.52$ mW. Why this step? Setting $α = 1$ is the maximum activity case, so this is the largest dynamic power this node can produce — the opposite extreme to step 1.
Total at $α = 1$ : $11.52 mW + 2.4 nW \approx 11.52$ mW (leakage negligible here). Why this step? Adding the two terms shows that at full activity the leakage is roughly a millionth of dynamic, so it drops out of any practical estimate — the mirror image of step 3.

Verify: At the $α = 0$ limit the answer is not zero — leakage remains, exactly the point of static power ✓. At $α = 1$ dynamic dwarfs static by $\sim 1 0^{6} \times$ ✓.

Cell E — Short-circuit term & its cutoff

Worked example E1: Does shoot-through fire or not?

Using the parent's inverter approximation $P_{sc} \approx \frac{β}{12} (V_{dd} - 2 V_{t h})^{3} τ f,$ two new symbols appear. In plain words:

$β$ ::: the transistor drive-strength (gain) factor in amps per volt² — how much current the device can push for a given gate over-drive; bigger, wider transistors have larger $β$ .
$τ$ ::: the signal transition time in seconds — how long the input takes to swing from 0 to $V_{dd}$ (see Signal Transition Time). Both transistors overlap-conduct only during this window, so a longer $τ$ means more shoot-through.
$V_{t h}$ ::: the threshold voltage — the gate voltage a transistor needs before it turns on.

Compare two designs. Both have $β = 1 \times 1 0^{- 3}$ A/V², $τ = 50$ ps, $f = 1$ GHz, $V_{t h} = 0.35$ V. (i) $V_{dd} = 1.0$ V. (ii) $V_{dd} = 0.6$ V.

Forecast: in case (ii), is $V_{dd} - 2 V_{t h}$ positive or negative — and what does that mean physically?

This is the lavender E tile — again a voltage lever, but on the shoot-through term with a hard cutoff.

Case (i): compute the gap. $V_{dd} - 2 V_{t h} = 1.0 - 0.70 = 0.30$ V $> 0$ . Why this step? Shoot-through only happens if the supply can turn both transistors on together, which needs $V_{dd} > 2 V_{t h}$ .
Plug in. $P_{sc} = \frac{1 0 ^{- 3}}{12} (0.30)^{3} (50 \times 1 0^{- 12}) (1 0^{9}) .$ $(0.30)^{3} = 0.027$ ; $τ f = 50 \times 1 0^{- 12} \times 1 0^{9} = 0.05$ . $P_{sc} = \frac{1 0 ^{- 3}}{12} \times 0.027 \times 0.05 = 1.125 \times 1 0^{- 7} W = 112.5 nW .$ Why this step? With the gap confirmed positive, the formula is valid, so we substitute every value in base units to get an actual shoot-through power; grouping $τ f$ first keeps the arithmetic clean.
Case (ii): the cutoff. $V_{dd} - 2 V_{t h} = 0.6 - 0.70 = - 0.10$ V $< 0$ . Why this step? The formula would give a negative cube — physically impossible. The correct interpretation is: the two transistors are never on simultaneously, so $P_{sc} = 0$ , not a negative number.

Verify: Case (i) is a tiny fraction of typical switching power ✓. Case (ii) hits the $V_{dd} < 2 V_{t h}$ degenerate case: clamp to zero ✓. Lowering voltage kills shoot-through — a reason low-voltage design is clean.

Cell F — Static vs dynamic crossover

Worked example F1: When does leakage take over?

A block: $C = 20$ pF, $V_{dd} = 0.9$ V, $f = 2$ GHz, leakage $I_{leak} = 5$ mA (a large, hot modern node). Find the activity factor $α^{*}$ at which dynamic power equals static power.

Forecast: will the crossover $α$ be tiny or near 1?

This is the coral F tile — a ratio/balance question weighing dynamic against leakage.

Set the two equal. $α^{*} C V_{dd}^{2} f = V_{dd} I_{leak} .$ Why this step? "Crossover" literally means the two terms are equal; solve for the unknown $α$ .
Solve for $α^{*}$ . Cancel one $V_{dd}$ : $α^{*} = \frac{I _{leak}}{C V _{dd} f} .$ Why this step? Both sides share a factor of $V_{dd}$ , so cancelling it isolates the unknown $α^{*}$ with the fewest terms — algebra before arithmetic keeps the numbers small.
Plug in. $α^{*} = \frac{5 \times 1 0 ^{- 3}}{( 20 \times 1 0 ^{- 12} ) ( 0.9 ) ( 2 \times 1 0 ^{9} )} .$ Denominator $= 20 \times 1 0^{- 12} \times 0.9 \times 2 \times 1 0^{9} = 3.6 \times 1 0^{- 2}$ . $α^{*} = \frac{5 \times 1 0 ^{- 3}}{3.6 \times 1 0 ^{- 2}} = 0.1389.$ Why this step? Substituting the base-unit values into the isolated formula turns the symbolic crossover condition into a concrete activity threshold we can compare against real workloads.

Verify: For any $α < 0.139$ the chip is leakage-dominated — real idle CPUs sit here, which is why Power Gating Techniques cut $V_{dd}$ to whole blocks. $α^{*}$ is a valid fraction in $[0, 1]$ ✓.

Cell G — Real-world word problem

Worked example G1: Battery life from a power budget

A wearable SoC averages $P_{total} = 50$ mW. Battery holds $E = 1.5$ watt-hours (Wh). How many hours does it run? Then: Dynamic Voltage Frequency Scaling (DVFS) cuts $V_{dd}$ from 1.0 V to 0.8 V. The 50 mW splits as 40 mW dynamic + 10 mW static. What is the new runtime?

Forecast: a 20% voltage cut — will runtime rise by more or less than 20%?

This is the mint G tile — the real-world word problem translating watts into hours.

Baseline runtime. $t = E / P = 1.5 Wh /0.050 W = 30$ hours. Why this step? Energy ÷ power = time; watt-hours ÷ watts = hours directly.
Split the power. Dynamic $= 40$ mW; static $= 10$ mW. Why this step? The two terms scale differently with voltage, so we must track them separately — this is exactly the correction the reviewer asked for.
Scale dynamic — quadratic. $(\frac{0.8}{1.0})^{2} = 0.64$ , so new dynamic $= 0.64 \times 40 = 25.6$ mW. Why this step? $P_{dynamic} \propto V_{dd}^{2}$ .
Scale static — linear. Since $P_{static} = V_{dd} I_{leak}$ and $I_{leak}$ is (to first order) fixed, static scales linearly with $V_{dd}$ : factor $\frac{0.8}{1.0} = 0.8$ , so new static $= 0.8 \times 10 = 8$ mW. Why this step? Holding static constant would contradict $P_{static} = V_{dd} I_{leak}$ ; the formula demands it drops with $V_{dd}$ . (Real leakage current also falls with voltage, so this is a conservative estimate.)
New total & runtime. $P^{'} = 25.6 + 8 = 33.6$ mW; $t^{'} = 1.5/0.0336 = 44.64$ hours. Why this step? Runtime depends on the combined draw, so we must re-add the two separately-scaled terms before dividing energy by power — scaling one term alone would give a wrong battery life.

Verify: Runtime rose from 30 h to $\approx 44.6$ h, a $\approx 49%$ gain from a 20% voltage cut — the quadratic dynamic term dominates the saving ✓. Units: Wh/W = h ✓.

Cell H — Static power's linear voltage scaling

Worked example H1: Leakage falls only linearly

A dark (idle) chip block leaks $I_{leak} = 4$ mA, essentially independent of small voltage changes. It runs at $V_{1} = 1.0$ V. Compute its static power, then the static power after dropping to $V_{2} = 0.7$ V. Compare the fractional drop to what a dynamic term would give.

Forecast: a 30% voltage cut — does leakage power fall by 30% or by more (like dynamic would)?

This is the butter H tile — the leakage lever, showing its linear voltage law.

Static at 1.0 V. $P_{static, 1} = V_{1} I_{leak} = 1.0 \times 4 \times 1 0^{- 3} = 4 \times 1 0^{- 3}$ W $= 4$ mW. Why this step? Direct application of $P_{static} = V_{dd} I_{leak}$ — leakage has no $α$ , $C$ , or $f$ .
Static at 0.7 V. $P_{static, 2} = 0.7 \times 4 \times 1 0^{- 3} = 2.8 \times 1 0^{- 3}$ W $= 2.8$ mW. Why this step? Only $V_{dd}$ changed and it appears to the first power, so the ratio is $\frac{0.7}{1.0} = 0.7$ — a plain linear scaling.
Compare with dynamic. A dynamic term over the same cut would scale by $0. 7^{2} = 0.49$ . Static scaled by $0.7$ . Why this step? Highlights the key edge case: leakage is linear in $V_{dd}$ , so voltage scaling helps static power less than it helps dynamic power.

Verify: Static fell by $1 - 0.7 = 30%$ — exactly the voltage cut, confirming linear (not quadratic) dependence ✓. Dynamic would have fallen $51%$ . This is why chips that idle a lot lean on Power Gating Techniques (which cut $I_{leak}$ to zero) rather than voltage alone.

Cell I — Exam twist

Worked example I1: DVFS scales voltage AND frequency together

A core at $V_{1} = 1.0$ V, $f_{1} = 3$ GHz uses $P_{1} = 12$ W dynamic power. To save energy, DVFS drops it to $V_{2} = 0.8$ V and, to keep timing valid, also lowers frequency to $f_{2} = 2.1$ GHz. Find the new dynamic power.

Forecast: two cuts stack multiplicatively — guess whether power more than halves.

This is the lavender I tile — the exam twist, pulling voltage and frequency levers at once.

Combined ratio. Only $V$ and $f$ change: $\frac{P _{2}}{P _{1}} = (\frac{V _{2}}{V _{1}})^{2} \cdot \frac{f _{2}}{f _{1}} .$ Why this step? $α, C$ are constant; the formula's $V^{2} f$ factor tells us exactly which powers to raise the ratios to.
Voltage part. $(\frac{0.8}{1.0})^{2} = 0.64$ . Why this step? We evaluate each lever's ratio separately so their contributions to the total drop are visible before combining.
Frequency part. $\frac{2.1}{3.0} = 0.70$ . Why this step? Frequency is linear, so its ratio enters to the first power — computing it alone lets us see how much of the saving comes from the clock versus the voltage.
Multiply. $0.64 \times 0.70 = 0.448$ . Why this step? Independent scaling factors multiply, so the combined effect is the product — this is why coupling two DVFS levers saves more than either alone.
Scale. $P_{2} = 0.448 \times 12 = 5.376$ W. Why this step? Multiplying the combined ratio by the known $P_{1}$ converts the fractional drop back into absolute watts.

Verify: Power fell to about 45% of original — more than half saved from modest cuts, because the two effects compound ✓. This is why DVFS pairs voltage and frequency reductions rather than doing either alone.

Recall Self-check

If activity factor is 0, is total power zero? ::: No — dynamic power is zero but static (leakage) power remains. A 20% voltage cut reduces switching power by how much? ::: About 36% (factor $0. 8^{2} = 0.64$ ). A 30% voltage cut reduces static power by how much? ::: Exactly 30% — static is linear in $V_{dd}$ . When does short-circuit power become exactly zero? ::: When $V_{dd} < 2 V_{t h}$ ; clamp the formula to 0, never negative.

See also: CMOS Inverter Design · Thermal Design Power (TDP) · FinFET Transistors · Subthreshold Slope · Signal Transition Time · Amdahl's Law