Exercises — Dynamic vs static power consumption

• (a) higher $f$ → appears only in $P_{\text{sw}}=\alpha C{V}_{dd}^{2}f$ → raises dynamic power.
• (b) higher $I_{\text{leak}}$ → appears only in $P_{\text{static}}=V_{dd}{I}_{\text{leak}}$ → raises static power.
• (c) higher $\alpha$ → more cycles actually switch → raises dynamic power.
• (d) clock stopped means $f=0$, so $P_{\text{sw}}=0$, but leakage never stops → only static power remains. This is exactly why an idle phone still drains its battery.

$V_{dd}$ is squared in the dynamic/switching formula, $P_{\text{sw}}=\alpha C{V}_{dd}^{2}f$. It is squared because charging a capacitor to voltage $V_{dd}$ costs energy $C{V}_{dd}^2$ per cycle — one $V_{dd}$ for the amount of charge $Q=C{V}_{dd}$, another $V_{dd}$ for the "height" that charge is pushed up to. In the static formula it appears to the first power only ($P_{\text{static}}=V_{dd}{I}_{\text{leak}}$), because it is just voltage times a leaking current.

$P_{\text{sw}}=\alpha C{V}_{dd}^{2}f=0.15\times (5\times 10^{-12})\times (1.1{)}^2\times (2\times 10^9)$ Group the prefixes first: $10^{-12}\times 10^9=10^{-3}$ (milli). Numbers: $0.15\times 5\times 1.21\times 2=1.815$. $P_{\text{sw}}=1.815\times 10^{-3}\text{W}\approx 1.82\text{mW}$

$P_{\text{static}}=V_{dd}{I}_{\text{leak}}=1.0\times (50\times 10^{-3})=0.05\text{W}=50\text{mW}$ Note this burns even with the clock stopped — a pure leakage tax.

Power is linear in $f$, so doubling $f$ doubles $P_{\text{sw}}$: $P_{\text{sw,new}}=2\times 1.815\text{mW}=3.63\text{mW}$ Factor of change: $\times 2$.

Only $V_{dd}$ changes, and $P_{\text{sw}}\propto V_{dd}^2$, so take the ratio: $\frac{P_2}{P_1}={\left(\frac{0.8}{1.2}\right)}^2={\left(\frac{2}{3}\right)}^2=\frac{4}{9}\approx 0.4444$ $P_2=0.4444\times 3.0=1.333\text{W}$ A 33% voltage cut → 56% power cut. This quadratic leverage is the heart of Dynamic Voltage Frequency Scaling (DVFS).

Halting the clock sets $f=0$, so $P_{\text{sw}}=\alpha C{V}_{dd}^2\cdot 0=0$. Static power does not depend on $f$, so it is unchanged: $P_{\text{total,idle}}=0+10=10\text{W}$ To kill that last 10 W you must remove the rail entirely — that is what Power Gating Techniques do.

$C$ and $f$ cancel in the ratio: $\frac{P_A}{P_B}=\frac{{\alpha }_A{V}_A^2}{{\alpha }_B{V}_B^2}=\frac{0.30\times 1.0^2}{0.10\times 1.3^2}=\frac{0.30}{0.10\times 1.69}=\frac{0.30}{0.169}\approx 1.775$ Design A dissipates ~1.78× more. The higher activity beats the lower voltage here — you must weigh both factors, not eyeball one.

Now both $V_{dd}^2$ and $f$ change: $\frac{P_2}{P_1}={\left(\frac{V_2}{V_1}\right)}^2\cdot \frac{f_2}{f_1}={\left(\frac{0.9}{1.2}\right)}^2\cdot \frac{2.0}{3.0}$ $=(0.75{)}^2\times 0.6667=0.5625\times 0.6667=0.375$ So $P_2=0.375P_1$ — a 62.5% reduction. The voltage term does most of the work; the frequency term adds a further linear cut.

Switching term ($\propto V^2$): $P_{\text{sw}}^{\prime }=20\times {\left(\frac{0.7}{1.0}\right)}^2=20\times 0.49=9.8\text{W}$ Static term ($\propto V_{dd}$ here, $I_{\text{leak}}$ held fixed): $P_{\text{static}}^{\prime }=5\times \frac{0.7}{1.0}=3.5\text{W}$ Total: $P^{\prime }=9.8+3.5=13.3\text{W}$ Down from 25 W — but notice static's share grew from $5/25=20\%$ to $3.5/13.3\approx 26\%$. As you scale voltage, leakage becomes a relatively bigger problem. (In real silicon leakage falls slower than this because $I_{\text{leak}}$ itself depends on threshold effects — see Subthreshold Slope.)

(a) $10^{-9}\times 10^9=10^0=1$ (nano × giga cancel completely): $P_{\text{sw}}=0.1\times (2\times 10^{-9})\times 1.0^2\times (1.5\times 10^9)=0.1\times 2\times 1.5=0.3\text{W}$ (b) $P_{\text{total}}=P_{\text{sw}}+P_{\text{static}}=0.3+0.3=0.6\text{W}$ (c) $\text{Headroom}=\text{TDP}-P_{\text{total}}=4-0.6=3.4\text{W}$ Plenty of thermal room — this SoC could clock up (raise $f$) or run more cores before hitting TDP.

New switching power — scale from the 0.3 W baseline by each changed factor: $P_{\text{sw}}^{\prime }=0.3\times \underset{\alpha :4\times }{\underbrace{\frac{0.4}{0.1}}}\times \underset{V^2:1.44\times }{\underbrace{{\left(\frac{1.2}{1.0}\right)}^2}}\times \underset{f:1.667\times }{\underbrace{\frac{2.5}{1.5}}}$ $=0.3\times 4\times 1.44\times 1.6667=0.3\times 9.6=2.88\text{W}$ Total: $P_{\text{total}}^{\prime }=2.88+0.36=3.24\text{W}$ $3.24\text{W}<4\text{W}$ → within TDP, with $0.76$ W headroom. If activity climbed further the governor would have to throttle (drop $V_{dd}$/$f$) to stay under budget — the classic thermal-throttling loop.

• Cutting $\alpha$ or $f$ by 20% → linear → power becomes $0.8\times$ → 20% cut.
• Cutting $V_{dd}$ by 20% → quadratic → power becomes $(0.8{)}^2=0.64\times$ → 36% cut. Voltage wins, because it is the only knob that enters squared. This is precisely why every low-power technique reaches for voltage scaling first (see Dynamic Voltage Frequency Scaling (DVFS)), accepting the frequency drop it forces as a fair trade.

Why is voltage the most powerful knob for cutting switching power? ::: Because it enters $P_{\text{sw}}=\alpha C{V}_{dd}^{2}f$ squared, while $\alpha$ and $f$ are only linear. What single change removes switching power but not leakage? ::: Stopping the clock ($f=0$) — leakage is independent of $f$. What does TDP actually specify? ::: The cooling budget (sustained heat the cooler must remove), not the instantaneous power draw.