Exercises — Dynamic vs static power consumption

• (a) higher $f$ → sirf only $P_{\text{sw}}=\alpha C{V}_{dd}^{2}f$ mein aata hai → dynamic power badhata hai.
• (b) higher $I_{\text{leak}}$ → sirf only $P_{\text{static}}=V_{dd}{I}_{\text{leak}}$ mein aata hai → static power badhata hai.
• (c) higher $\alpha$ → zyada cycles actually switch karte hain → dynamic power badhata hai.
• (d) clock stopped matlab $f=0$, toh $P_{\text{sw}}=0$, lekin leakage kabhi nahi rukti → sirf static power bachti hai. Yahi wajah hai ki ek idle phone phir bhi apni battery drain karta hai.

$V_{dd}$ dynamic/switching formula mein squared hai, $P_{\text{sw}}=\alpha C{V}_{dd}^{2}f$. Yeh squared isliye hai kyunki ek capacitor ko $V_{dd}$ voltage tak charge karne mein energy lagti hai $C{V}_{dd}^2$ per cycle — ek $V_{dd}$ charge ki quantity ke liye $Q=C{V}_{dd}$, doosra $V_{dd}$ us "height" ke liye jahan charge ko push kiya jaata hai. Static formula mein yeh sirf first power par aata hai ($P_{\text{static}}=V_{dd}{I}_{\text{leak}}$), kyunki woh sirf voltage times ek leaking current hai.

$P_{\text{sw}}=\alpha C{V}_{dd}^{2}f=0.15\times (5\times 10^{-12})\times (1.1{)}^2\times (2\times 10^9)$ Pehle prefixes group karo: $10^{-12}\times 10^9=10^{-3}$ (milli). Numbers: $0.15\times 5\times 1.21\times 2=1.815$. $P_{\text{sw}}=1.815\times 10^{-3}\text{W}\approx 1.82\text{mW}$

$P_{\text{static}}=V_{dd}{I}_{\text{leak}}=1.0\times (50\times 10^{-3})=0.05\text{W}=50\text{mW}$ Note karo yeh clock stopped rehne par bhi burn hoti hai — ek pure leakage tax.

Power $f$ mein linear hai, toh $f$ double karne par $P_{\text{sw}}$ double ho jaati hai: $P_{\text{sw,new}}=2\times 1.815\text{mW}=3.63\text{mW}$ Change ka factor: $\times 2$.

Sirf $V_{dd}$ change ho raha hai, aur $P_{\text{sw}}\propto V_{dd}^2$, toh ratio lo: $\frac{P_2}{P_1}={\left(\frac{0.8}{1.2}\right)}^2={\left(\frac{2}{3}\right)}^2=\frac{4}{9}\approx 0.4444$ $P_2=0.4444\times 3.0=1.333\text{W}$ 33% voltage cut → 56% power cut. Yeh quadratic leverage Dynamic Voltage Frequency Scaling (DVFS) ka heart hai.

Clock halt karna $f=0$ set karta hai, toh $P_{\text{sw}}=\alpha C{V}_{dd}^2\cdot 0=0$. Static power $f$ par depend nahi karti, toh woh unchanged rehti hai: $P_{\text{total,idle}}=0+10=10\text{W}$ Us last 10 W ko khatam karne ke liye rail completely remove karni padegi — yahi Power Gating Techniques karta hai.

$C$ aur $f$ ratio mein cancel ho jaate hain: $\frac{P_A}{P_B}=\frac{{\alpha }_A{V}_A^2}{{\alpha }_B{V}_B^2}=\frac{0.30\times 1.0^2}{0.10\times 1.3^2}=\frac{0.30}{0.10\times 1.69}=\frac{0.30}{0.169}\approx 1.775$ Design A ~1.78× zyada dissipate karta hai. Higher activity yahan lower voltage ko beat kar deti hai — tumhe dono factors weigh karne chahiye, sirf ek ko eyeball nahi karna.

Ab dono $V_{dd}^2$ aur $f$ change hote hain: $\frac{P_2}{P_1}={\left(\frac{V_2}{V_1}\right)}^2\cdot \frac{f_2}{f_1}={\left(\frac{0.9}{1.2}\right)}^2\cdot \frac{2.0}{3.0}$ $=(0.75{)}^2\times 0.6667=0.5625\times 0.6667=0.375$ Toh $P_2=0.375P_1$ — ek 62.5% reduction. Voltage term zyaadatar kaam karta hai; frequency term aur ek linear cut add karta hai.

Switching term ($\propto V^2$): $P_{\text{sw}}^{\prime }=20\times {\left(\frac{0.7}{1.0}\right)}^2=20\times 0.49=9.8\text{W}$ Static term ($\propto V_{dd}$ yahan, $I_{\text{leak}}$ fixed raha): $P_{\text{static}}^{\prime }=5\times \frac{0.7}{1.0}=3.5\text{W}$ Total: $P^{\prime }=9.8+3.5=13.3\text{W}$ 25 W se neeche — lekin notice karo ki static ka share badh gaya $5/25=20\%$ se $3.5/13.3\approx 26\%$ tak. Jab tum voltage scale karte ho, leakage relatively bada problem ban jaata hai. (Real silicon mein leakage isse slow girta hai kyunki $I_{\text{leak}}$ khud threshold effects par depend karta hai — Subthreshold Slope dekho.)

(a) $10^{-9}\times 10^9=10^0=1$ (nano × giga completely cancel ho jaate hain): $P_{\text{sw}}=0.1\times (2\times 10^{-9})\times 1.0^2\times (1.5\times 10^9)=0.1\times 2\times 1.5=0.3\text{W}$ (b) $P_{\text{total}}=P_{\text{sw}}+P_{\text{static}}=0.3+0.3=0.6\text{W}$ (c) $\text{Headroom}=\text{TDP}-P_{\text{total}}=4-0.6=3.4\text{W}$ Kafi thermal room hai — yeh SoC clock up kar sakta hai ($f$ badhao) ya zyada cores run kar sakta hai TDP hit karne se pehle.

Nayi switching power — 0.3 W baseline se har changed factor se scale karo: $P_{\text{sw}}^{\prime }=0.3\times \underset{\alpha :4\times }{\underbrace{\frac{0.4}{0.1}}}\times \underset{V^2:1.44\times }{\underbrace{{\left(\frac{1.2}{1.0}\right)}^2}}\times \underset{f:1.667\times }{\underbrace{\frac{2.5}{1.5}}}$ $=0.3\times 4\times 1.44\times 1.6667=0.3\times 9.6=2.88\text{W}$ Total: $P_{\text{total}}^{\prime }=2.88+0.36=3.24\text{W}$ $3.24\text{W}<4\text{W}$ → TDP ke andar, $0.76$ W headroom ke saath. Agar activity aur badhti toh governor ko throttle karna padta ($V_{dd}$/$f$ drop karo) budget ke andar rehne ke liye — yeh classic thermal-throttling loop hai.

• $\alpha$ ya $f$ 20% cut karna → linear → power $0.8\times$ ho jaati hai → 20% cut.
• $V_{dd}$ 20% cut karna → quadratic → power $(0.8{)}^2=0.64\times$ ho jaati hai → 36% cut. Voltage jeetta hai, kyunki yeh akela knob hai jo squared enter karta hai. Yahi wajah hai ki har low-power technique pehle voltage scaling ke liye reach karti hai (dekho Dynamic Voltage Frequency Scaling (DVFS)), jo frequency drop ko fair trade maankar accept karti hai.

Voltage switching power cut karne ka sabse powerful knob kyun hai? ::: Kyunki yeh $P_{\text{sw}}=\alpha C{V}_{dd}^{2}f$ mein squared enter karta hai, jabki $\alpha$ aur $f$ sirf linear hain. Kaun sa single change switching power remove karta hai lekin leakage nahi? ::: Clock rokna ($f=0$) — leakage $f$ se independent hai. TDP actually kya specify karta hai? ::: Cooling budget (sustained heat jo cooler ko remove karni hai), instantaneous power draw nahi.