6.4.1 · D5Power, Thermal & Reliability
Question bank — Dynamic vs static power consumption
This page hunts down the misconceptions that this topic invites. Each line is a Question ::: Answer reveal — read the question, commit to an answer, then uncover. The parent build-up lives in Dynamic vs static power consumption; but you should not need to leave this page — the symbols and pictures you need are all restated below.
The figure above is the mental picture behind almost every trap on this page: dynamic power is the two-way flow of charge into and out of the bucket (blue in, red out), while static power is the small leak that drips regardless (green). Keep pointing back to it.
True or false — justify
Every one of these is a sentence you might feel is right. Decide true/false and give the reason before revealing.
Doubling the clock frequency doubles the switching power.
True — switching power is linear in , so twice the switching events per second means twice the energy per second, all else fixed.
Doubling the clock frequency doubles the total chip power.
False — only dynamic power scales with ; static (leakage, the green drip in the figure) flows whether or not anything switches, so total power grows by less than 2×.
Halving the supply voltage halves the switching power.
False — switching power depends on , so halving voltage cuts switching power to one quarter, a 4× reduction, not 2×.
Static power is zero when the circuit is doing no useful work.
False — "idle" transistors still leak (subthreshold, gate-tunneling, junction currents); static power is precisely the power burned while nothing switches.
The energy the supply delivers to charge a capacitor equals the energy stored in it.
False — supply delivers but only is stored; the other half is dissipated as heat in the channel resistance during the charge (see the split in the energy figure below).
Short-circuit current charges the load capacitor just like switching current does.
False — short-circuit (shoot-through) current flows straight from to ground through both partially-on transistors; it never reaches the bucket , so it is a separate wasted term.
Activity factor can exceed 1 for a very busy circuit.
False — is the fraction of clock cycles in which a node switches, so it lives in ; a node can switch at most once per cycle.
If we could make transistor resistance zero, charging a capacitor would dissipate no heat.
False (and surprising) — the charging loss is independent of the resistance value; a smaller resistor just dumps the same energy faster. Only slower voltage ramps (adiabatic charging) reduce it.
Leakage power is a bigger worry on old large-node chips than on modern tiny-node chips.
False — smaller nodes have thinner oxides and lower thresholds, so subthreshold and tunneling leakage grow; static power became a dominant concern precisely at advanced nodes.
Short-circuit power is proportional to just like switching power.
False — the standard inverter approximation makes it scale as , a cubic in the overdrive, so it collapses far faster than switching power as voltage drops.
Where the energy goes (charging a capacitor)
The bar shows the trap in the fifth true/false line above: the supply pays the full (whole bar), the capacitor keeps only the top half (green), and the bottom half (red) is burned as heat in the channel — no matter how good the transistor is. Discharge then dumps the stored green half to ground as well, so a full 0→1→0 cycle costs the whole .
The shoot-through window (why the cubic appears)
Spot the error
Each line contains a plausible-sounding statement with exactly one flaw. Name the flaw.
", so power is linear in voltage."
The voltage term is wrong — it must be . Each cycle moves energy , and the missing square is where the whole DVFS advantage comes from.
"Because charging dissipates and discharging dissipates nothing, energy per full cycle is ."
Discharging is not free — the stored (green half in the energy figure) is dumped to ground through the pull-down, so the full 0→1→0 cycle costs .
"Short-circuit power vanishes only when ."
It vanishes whenever , because the two "on" bands in the shoot-through figure never overlap — there is no window where both transistors conduct.
"To cut dynamic power, sharpen the input edges to reduce ."
Sharpening edges (smaller transition time ) reduces the short-circuit term by narrowing the time spent in the overlap window, not . Activity factor is set by how often the logic actually toggles, not by edge speed.
"Leakage current is a linear function of threshold voltage, so lowering a little only leaks a little more."
Subthreshold leakage is exponential in threshold voltage; a small drop can multiply leakage several-fold.
"A single cache line burns 6 mW, so a chip with a million such nodes burns 6 mW total."
Power adds across switching nodes — a million nodes burn on the order of kilowatts of that toy figure; real chips stay bounded because and node capacitances are far smaller than the worst case.
"DVFS saves power by lowering voltage, and frequency can stay the same."
Lower voltage slows transistors, so timing margins force frequency down too. The real saving mixes the and terms; you cannot hold fixed at an arbitrarily low voltage.
Why questions
The reasoning is the answer here — a bare fact earns nothing.
Why does the factor of appear in stored energy but not in supply energy?
The supply pushes charge at the full constant , so work is ; the capacitor's own voltage climbs from 0 to , averaging , so it only stores — exactly the split drawn in the energy bar.
Why is voltage the first knob engineers reach for to cut dynamic power?
Because of the quadratic dependence — a modest voltage cut buys an outsized power cut (), a leverage no linear term like or offers.
Why does short-circuit current exist at all in a "digital" (0-or-1) circuit?
Real inputs are analog ramps of finite transition time , so mid-swing both the PMOS and NMOS are briefly on together (the overlap window in the shoot-through figure), opening a direct -to-ground path.
Why does static power matter more for a phone left idle than its dynamic power?
An idle phone barely switches, so dynamic power is near zero, but leakage (the green drip) keeps flowing every nanosecond — over hours of standby, that constant trickle dominates battery drain, motivating power gating.
Why is load capacitance something designers fight to shrink even though it's "just" linear in the formula?
is the size of the bucket in the first figure and it multiplies every dynamic term across billions of nodes; shrinking it scales the whole chip's dynamic budget, and unlike voltage it carries no timing penalty.
Why can't we simply set extremely low to nearly eliminate all power?
Below a point the gate can't reliably overcome , switching slows drastically (frequency must crash), noise margins collapse, and subthreshold leakage's exponential character can make static power rise relative to the shrinking dynamic budget.
Why do FinFET transistors help the power story?
Their gate wraps the channel on multiple sides, tightening electrostatic control, which steepens the subthreshold slope and slashes the leakage current — attacking the static (green-drip) term directly.
Why does Thermal Design Power care about the sum of dynamic and static power rather than either alone?
TDP sizes the cooling for total heat delivered; both terms convert electrical energy to heat, so the heatsink must handle switching heat plus the ever-present leakage floor.
Edge cases
The formulas hide their assumptions at the boundaries. These probe them.
What is the dynamic power of a node that never switches ()?
Zero dynamic power — no charging, no discharging, no shoot-through — but it still burns static leakage power as long as it is powered.
What happens to short-circuit power exactly at ?
It reaches zero — the factor becomes , meaning the overlap window in the shoot-through figure has just closed to zero width.
If a node toggles every single clock cycle, what is and is that realistic?
, its maximum. Real logic rarely toggles every node every cycle, so system-wide typically sits around 0.1–0.3.
At (a perfectly stopped clock), what power remains?
All dynamic terms carry a factor , so they vanish — only static leakage (green drip) survives, which is exactly the reasoning behind clock-gating and power gating.
If input transition time (infinitely sharp edges), what happens to short-circuit power?
It tends to zero — with no time spent mid-swing, the both-on window closes, so the shoot-through charge per transition vanishes.
Two designs have identical dynamic power but one has half the leakage; which wins on battery for a mostly-idle device?
The low-leakage design, decisively — for a device that spends most time idle, static power sets the standby drain, and dynamic power barely enters the average.
Recall One-line self-test
Which single term survives when the clock stops, and which term carries the ? ::: Static (leakage) power — the green drip — survives a stopped clock; the switching component of dynamic power carries the (short-circuit carries ).