Dynamic vs static power consumption: Question bank

6.4.1 · D5 · Hardware › Power, Thermal & Reliability › Dynamic vs static power consumption

Yeh page un misconceptions ko pakadti hai jo yeh topic invite karta hai. Har line ek Question ::: Answer reveal hai — pehle question padho, apna answer socho, phir uncover karo. Parent build-up Dynamic vs static power consumption mein hai; lekin tumhe yeh page chhodni nahi chahiye — jo symbols aur pictures chahiye woh sab neeche restate kiye gaye hain.

Figure — Dynamic vs static power consumption

Upar wala figure is page par almost har trap ke peeche ka mental picture hai: dynamic power charge ka woh do-taraf flow hai jo bucket $C$ mein jaata aur nikalta hai (blue in, red out), jabki static power woh chhoti si leak hai jo chahe kuch bhi ho drip karta rehta hai (green). Isko baar baar dekhte rehna.

True or false — justify

Inme se har ek woh sentence hai jo tumhe sahi lagti hai. True/false decide karo aur reason bhi do reveal karne se pehle.

Doubling the clock frequency

f

doubles the switching power.

True — switching power

α C V_{dd}^{2} f

f

mein linear hai, isliye per second double switching events matlab double energy per second, baaki sab same rehne par.

Clock frequency double karne se total chip power double ho jaata hai.

False — sirf dynamic power

f

ke saath scale karta hai; static (leakage, figure mein green drip) chahe kuch switch ho ya na ho flow karta rehta hai, isliye total power 2× se kam badhta hai.

Supply voltage

V_{dd}

half karne se switching power half ho jaata hai.

False — switching power

V_{dd}^{2}

par depend karta hai, isliye voltage half karne se switching power ek quarter ho jaata hai, yaani 4× reduction, 2× nahi.

Jab circuit koi useful kaam nahi kar raha tab static power zero hoti hai.

False — "idle" transistors abhi bhi leak karte hain (subthreshold, gate-tunneling, junction currents); static power precisely woh power hai jo tab burn hoti hai jab kuch bhi switch nahi karta.

Supply jo energy capacitor charge karne ke liye deliver karta hai woh us mein stored energy ke barabar hoti hai.

False — supply

C V_{dd}^{2}

deliver karta hai lekin sirf

\frac{1}{2} C V_{dd}^{2}

store hoti hai; doosra aadha charge ke dauran channel resistance mein heat ke roop mein dissipate ho jaata hai (neeche energy figure mein split dekho).

Short-circuit current load capacitor ko exactly waise hi charge karta hai jaise switching current karta hai.

False — short-circuit (shoot-through) current directly

V_{dd}

se ground tak dono partially-on transistors ke through flow karta hai; yeh kabhi bucket

C

tak nahi pahunchta, isliye yeh ek alag wasted term hai.

Bahut busy circuit ke liye activity factor

α

1 se zyada ho sakta hai.

False —

α

un clock cycles ka fraction hai jisme ek node switch karta hai, isliye yeh

[0, 1]

mein rehta hai; ek node per cycle zyada se zyada ek baar switch ho sakta hai.

Agar hum transistor resistance zero kar sakein, toh capacitor charge karna koi heat dissipate nahi karega.

False (aur surprising) —

\frac{1}{2} C V_{dd}^{2}

charging loss resistance value se independent hai; chhota resistor sirf same energy ko faster dump karta hai. Sirf slower voltage ramps (adiabatic charging) isko reduce karte hain.

Leakage power purane large-node chips par modern tiny-node chips se zyada badi chinta hai.

False — chhote nodes mein thinner oxides aur lower thresholds hote hain, isliye subthreshold aur tunneling leakage badhti hai; static power precisely advanced nodes par ek dominant concern ban gayi.

Short-circuit power

V_{dd}^{2}

ke proportional hai bilkul switching power ki tarah.

False — standard inverter approximation isko

(V_{dd} - 2 V_{t h})^{3}

ke roop mein scale karati hai, overdrive mein ek cubic, isliye yeh switching power se kahin zyada tezi se collapse karta hai jaise voltage girta hai.

Energy kahan jaati hai (capacitor charge karna)

Bar upar wali paanchvi true/false line mein trap dikhata hai: supply poora $C V_{dd}^{2}$ pay karta hai (puri bar), capacitor sirf upar wala aadha $\frac{1}{2} C V_{dd}^{2}$ rakhta hai (green), aur neeche ka aadha (red) channel mein heat ke roop mein burn ho jaata hai — chahe transistor kitna bhi achha ho. Phir discharge stored green half ko bhi ground par dump kar deta hai, isliye ek poora 0→1→0 cycle poora $C V_{dd}^{2}$ cost karta hai.

Shoot-through window (cubic kyun aata hai)

Intuition Short-circuit power

$(V_{dd} - 2 V_{t h})^{3}$ ke roop mein kyun scale karta hai Figure dekho. Jaise input 0 se $V_{dd}$ tak ramp karta hai, NMOS on hota hai jaise hi input $V_{t h}$ cross karta hai, aur PMOS tab tak on rehta hai jab tak input $V_{dd} - V_{t h}$ tak nahi pahunch jaata. Overlap window — jahan dono conduct karte hain aur current seedha through shoot karta hai — exactly $V_{dd} - 2 V_{t h}$ width ka input band hai (shaded). Is band ke saath do effects badhti hain: current spike taller hoti hai (roughly $\propto (V_{dd} - 2 V_{t h})^{2}$ , square-law transistor current) aur window time mein wider hoti hai ( $\propto (V_{dd} - 2 V_{t h})$ ). Height × width multiply karo aur tumhe cubic $(V_{dd} - 2 V_{t h})^{3}$ milta hai. Agar $V_{dd} \leq 2 V_{t h}$ ho toh dono "on" bands kabhi overlap nahi karte, window band ho jaati hai, aur term exactly zero ho jaata hai.

Error dhundho

Har line mein ek plausible-sounding statement hai jisme exactly ek flaw hai. Flaw batao.

P_{switching} = α C V_{dd} f

, isliye power voltage mein linear hai."

Voltage term galat hai — woh

V_{dd}^{2}

hona chahiye. Har cycle

C V_{dd}^{2}

energy move karta hai, aur missing square wahi hai jahan DVFS ka sara advantage aata hai.

"Kyunki charging

\frac{1}{2} C V_{dd}^{2}

dissipate karta hai aur discharging kuch nahi, isliye energy per full cycle

\frac{1}{2} C V_{dd}^{2}

hai."

Discharging free nahi hai — stored

\frac{1}{2} C V_{dd}^{2}

(energy figure mein green half) pull-down ke through ground par dump ho jaata hai, isliye poora 0→1→0 cycle

C V_{dd}^{2}

cost karta hai.

"Short-circuit power sirf tab vanish hoti hai jab

V_{dd} = 0

ho."

Yeh tab vanish hoti hai jab bhi

V_{dd} < 2 V_{t h}

ho, kyunki shoot-through figure mein dono "on" bands kabhi overlap nahi karte — koi window nahi hoti jahan dono transistors conduct karein.

"Dynamic power cut karne ke liye,

α

reduce karne ke liye input edges sharpen karo."

Edges sharpen karna (chhota transition time

τ

) overlap window mein bitaya gaya time narrow karke short-circuit term reduce karta hai,

α

nahi. Activity factor is baat se set hoti hai ki logic actually kitni baar toggle karta hai, edge speed se nahi.

"Leakage current threshold voltage ka linear function hai, isliye

V_{t h}

thoda kam karne se thoda hi zyada leak hoga."

Subthreshold leakage threshold voltage mein exponential hai; ek chhota

V_{t h}

drop leakage ko kai-fold multiply kar sakta hai.

"Ek single cache line 6 mW burn karta hai, isliye ek chip jisme ek million aise nodes hain woh total 6 mW burn karta hai."

Power switching nodes ke across add hoti hai — ek million nodes us toy figure ka kilowatts ke order mein burn karenge; real chips bounded rehti hain kyunki

α

aur node capacitances worst case se kahin chhote hain.

"DVFS power save karta hai voltage kaam karke, aur frequency same reh sakti hai."

Kam voltage transistors ko slow kar deta hai, isliye timing margins frequency ko bhi neeche laane par majboor karti hain. Real saving

V_{dd}^{2}

aur

f

dono terms ko mix karta hai; tum arbitrarily low voltage par

f

fix nahi rakh sakte.

Why questions

Yahan reasoning hi answer hai — ek bare fact se kuch nahi milta.

\frac{1}{2}

factor stored energy mein kyun aata hai lekin supply energy mein nahi?

Supply full constant

V_{dd}

par charge push karta hai, isliye kaam

V_{dd} \cdot Q = C V_{dd}^{2}

hai; capacitor ki apni voltage 0 se

V_{dd}

tak climb karti hai, average

V_{dd} /2

, isliye woh sirf

\frac{1}{2} C V_{dd}^{2}

store karta hai — exactly woh split jo energy bar mein draw hai.

Dynamic power cut karne ke liye engineers sabse pehle voltage ka knob kyun pakadते hain?

Kyunki quadratic dependence ki wajah se — ek modest voltage cut ek outsized power cut deti hai (

0.7 5^{2} = 0.56

), ek aise leverage jo koi linear term jaise

f

α

nahi de sakta.

"Digital" (0-or-1) circuit mein bhi short-circuit current exist kyun karta hai?

Real inputs finite transition time

τ

ke analog ramps hain, isliye mid-swing mein PMOS aur NMOS thodi der ke liye saath on rehte hain (shoot-through figure mein overlap window), ek direct

V_{dd}

-to-ground path kholte hain.

Ek mostly-idle phone ke liye static power uski dynamic power se zyada kyun matter karta hai?

Ek idle phone bahut kam switch karta hai, isliye dynamic power near zero hoti hai, lekin leakage (green drip) har nanosecond flow karta rehta hai — hours of standby par woh constant trickle battery drain dominate karta hai, power gating motivate karta hai.

Load capacitance

C

kuch designers shrink karne ke liye kyun ladte hain even though formula mein yeh "sirf" linear hai?

C

pehle figure mein bucket ka size hai aur yeh billions of nodes par har dynamic term ko multiply karta hai; isko shrink karna poore chip ke dynamic budget ko scale karta hai, aur voltage ke unlike iska koi timing penalty nahi hota.

Hum

V_{dd}

ko extremely low kyun nahi set kar sakte almost sari power eliminate karne ke liye?

Ek point ke neeche gate reliably

V_{t h}

overcome nahi kar sakta, switching drastically slow ho jaata hai (frequency crash karni padti hai), noise margins collapse ho jaate hain, aur subthreshold leakage ka exponential character static power ko shrinking dynamic budget ke relative rise kara sakta hai.

FinFET transistors power story mein help kyun karte hain?

Unka gate channel ko multiple sides par wrap karta hai, electrostatic control tight karta hai, jo subthreshold slope ko steepen karta hai aur leakage current slash karta hai — directly static (green-drip) term par attack karta hai.

Thermal Design Power dynamic aur static power ke sum ki kyun care karta hai, kisi ek ki jagah?

TDP cooling ko total heat deliver ke liye size karta hai; dono terms electrical energy ko heat mein convert karti hain, isliye heatsink ko switching heat plus ever-present leakage floor handle karni padti hai.

Edge cases

Formulas apne assumptions ko boundaries par chhupa lete hain. Yeh unhe probe karte hain.

Ek node jo kabhi switch nahi karta (

α = 0

) uski dynamic power kya hogi?

Zero dynamic power — koi charging nahi, koi discharging nahi, koi shoot-through nahi — lekin jab tak woh powered hai tab tak static leakage power burn hoti rehti hai.

V_{dd} = 2 V_{t h}

par exactly short-circuit power ka kya hoga?

Yeh zero ho jaati hai —

(V_{dd} - 2 V_{t h})^{3}

factor

0^{3}

ban jaata hai, matlab shoot-through figure mein overlap window ki width zero ho gayi hai.

Agar ek node har single clock cycle mein toggle kare, toh

α

kya hoga aur kya woh realistic hai?

α = 1

, uski maximum. Real logic mein nadran har cycle mein har node toggle hota hai, isliye system-wide

α

typically 0.1–0.3 ke aas paas hota hai.

f = 0

par (bilkul ruka hua clock), kaun si power bachti hai?

Sab dynamic terms mein

f

ka factor hota hai, isliye woh vanish ho jaate hain — sirf static leakage (green drip) bachti hai, jo exactly clock-gating aur power gating ke peeche reasoning hai.

Agar input transition time

τ \to 0

ho (infinitely sharp edges), short-circuit power ka kya hoga?

Yeh zero ki taraf tend karta hai — mid-swing mein koi waqt nahi bitaya, dono-on window band ho jaati hai, isliye per transition shoot-through charge vanish ho jaata hai.

Do designs identical dynamic power rakhte hain lekin ek ki leakage half hai; mostly-idle device ke liye battery par kaun jeeta hai?

Low-leakage design, decisively — ek device ke liye jo zyada waqt idle rehta hai, static power standby drain set karti hai, aur dynamic power average mein mushkil se enter karta hai.

Recall One-line self-test

Kaun sa single term tab bachta hai jab clock ruk jaata hai, aur kaun sa term $V_{dd}^{2}$ carry karta hai? ::: Static (leakage) power — green drip — ruke hue clock par bachta hai; dynamic power ka switching component $V_{dd}^{2}$ carry karta hai (short-circuit $(V_{dd} - 2 V_{t h})^{3}$ carry karta hai).