Dynamic vs static power consumption: Worked examples

6.4.1 · D3 · Hardware › Power, Thermal & Reliability › Dynamic vs static power consumption

Yeh page ek drill hai har us case ke liye jo dynamic/static power formulas mein aa sakta hai. Hum parent page ke do master formulas se shuru karte hain aur koi step assume nahi karte. Agar koi symbol aata hai, toh woh ya toh yahan define kiya gaya hai ya pehle 6.4.1 Dynamic vs static power consumption mein.

Recall Woh formulas jo hum har jagah use karenge

Dynamic power = do switching-related terms ko saath mein add karo: $P_{dynamic} = P_{switching} α C V_{dd}^{2} f + short-circuit P_{sc}$ Zyaadatar cases mein short-circuit term $P_{sc}$ chota hota hai, isliye hum aksar $P_{dynamic} \approx P_{switching} = α C V_{dd}^{2} f$ use karte hain; Cell E mein $P_{sc}$ explicitly handle kiya gaya hai. Static (leakage) power: $P_{static} = V_{dd} I_{leak}$ Total: $P_{total} = P_{dynamic} + P_{static}$ .

Meanings (plain words mein):

$α$ ::: activity factor — clock ticks ka woh fraction jisme ek node actually flip karta hai, 0 aur 1 ke beech
$C$ ::: load capacitance farads mein — kitna charge ek node ko voltage change karne ke liye move karna padta hai
$V_{dd}$ ::: supply voltage volts mein — woh "height" jitni charge pump ki jaati hai
$f$ ::: clock frequency hertz mein — flips per second
$I_{leak}$ ::: leakage current amps mein — "off" transistors se guzarne wali trickle
$P_{sc}$ ::: short-circuit (shoot-through) power — woh energy jo tab jalti hai jab dono transistors thodi der ke liye saath conduct karte hain

The scenario matrix

Har power question in case classes mein se ek (ya unka blend) hota hai. Neeche, har class ko kam se kam ek fully worked example milta hai, jise uske cell letter se tag kiya gaya hai.

Cell	Case class	Kya toot-ta hai / kya dekhna hai
A	Plain plug-in (saare values diye hain, non-zero)	unit prefixes pico/giga/milli cleanly cancel hone chahiye
B	Dynamic power ka voltage scaling (ratio question)	$V^{2}$ dominance — kabhi linear scale mat karo
C	Frequency scaling	$f$ mein linear — lekin real DVFS, $f$ ko $V$ se tie karta hai
D	Activity factor extremes ( $α = 0$ aur $α = 1$ )	$α = 0$ ⇒ dynamic vanish, sirf leakage bachti hai
E	Short-circuit term aur $V_{dd} < 2 V_{t h}$ cutoff	term zero ho jaati hai, negative nahi
F	Static vs dynamic crossover (idle chip)	low activity par kaun sa term jeetega?
G	Real-world word problem (battery / TDP)	watts → joules → hours translate karo; dono terms scale hote hain
H	Static power ki linear voltage scaling	$P_{static} \propto V_{dd}$ , $V_{dd}^{2}$ nahi
I	Exam twist (combined scaling + solve-for-unknown)	ek saath do variables change karo, ya formula invert karo

Neeche wali figure is poore page ka map hai: nau coloured tiles, ek har case class A–I ke liye. Jab tum har example work karo, apna letter tile par dhundho — tile colours worded steps mein reuse hote hain (lavender = voltage lever, coral = ratio/scaling lever, mint = frequency ya word-problem, butter = activity ya leakage) taaki ek nazar mein pata chale ki woh case kaun sa lever pull kar raha hai. Neeche ki caption formula notice karo: har tile bas $P_{total} = α C V_{dd}^{2} f + V_{dd} I_{leak}$ ke ek piece par stress daalne ka tarika hai.

Figure — Dynamic vs static power consumption

Cell A — Plain plug-in

Worked example A1: Single gate switching power

Ek logic gate mein $C = 5$ pF, $V_{dd} = 1.0$ V, $f = 2$ GHz, $α = 0.25$ hai. $P_{switching}$ nikalo.

Forecast: pehle order of magnitude guess karo — kya yeh microwatts hai ya watts?

Yeh example lavender A tile par hai — plain plug-in jo koi scaling lever nahi khichta.

Formula likho. $P = α C V_{dd}^{2} f$ . Yeh step kyun? Hum switching power maang rahe hain jisme saare chaar inputs diye hain, isliye yeh master formula hai, koi correction nahi chahiye.
Prefixes convert karo. $C = 5 \times 1 0^{- 12}$ F, $f = 2 \times 1 0^{9}$ Hz. Yeh step kyun? Pico ( $1 0^{- 12}$ ) aur giga ( $1 0^{9}$ ) base units mein hone chahiye taaki answer watts mein aaye.
Multiply karo. $P = 0.25 \times 5 \times 1 0^{- 12} \times (1.0)^{2} \times 2 \times 1 0^{9}$ $= 0.25 \times 5 \times 2 \times 1 0^{- 12 + 9} = 2.5 \times 1 0^{- 3} W = 2.5 mW$ Yeh step kyun? Numbers aur powers of ten ko alag-alag group karo: $1 0^{- 12} \cdot 1 0^{9} = 1 0^{- 3}$ = milli.

Verify karo: Units: $F \cdot V^{2} \cdot Hz = (C/V) \cdot V^{2} \cdot (1/ s) = C \cdot V / s = J/s = W$ ✓. "Milliwatts" ka order-of-magnitude guess sahi nikla.

Cell B — Voltage scaling of dynamic power

Worked example B1: Voltage girao, power girti dekho

Ek block $V_{1} = 1.0$ V par $P_{1} = 4.0$ W switching power burn karta hai. Hum isse $V_{2} = 0.8$ V par le jaate hain, $C$ , $f$ , $α$ fixed rakhte hue. Naya power?

Forecast: 20% voltage cut — kya tum 20% power cut expect karte ho, ya zyaada?

Yeh coral B tile hai — ek ratio question jo voltage lever khichta hai.

Ratio banao. Sirf $V_{dd}$ badla hai, isliye $\frac{P _{2}}{P _{1}} = (\frac{V _{2}}{V _{1}})^{2} .$ Yeh step kyun? $C, f, α$ cancel ho jaate hain kyunki dono cases mein identical hain — ratio voltage effect ko isolate karta hai.
Compute karo. $(\frac{0.8}{1.0})^{2} = 0.64$ . Yeh step kyun? Power voltage mein quadratic hai — yahi wajah hai ki Dynamic Voltage Frequency Scaling (DVFS) kaam karta hai.
Scale karo. $P_{2} = 0.64 \times 4.0 = 2.56$ W. Yeh step kyun? Ratio ne sirf original power ka fraction diya; $P_{1}$ se multiply karne par woh fraction watts mein ek absolute number banta hai.

Verify karo: 20% voltage cut ne $1 - 0.64 = 36%$ power cut diya — 20% se zyaada, jaisa quadratic predict karta hai. Sanity check: $P_{2} < P_{1}$ ✓. (Iska contrast Cell H se karo, jahan static power sirf linearly girta hai.)

Cell C — Frequency scaling

Worked example C1: Overclocking ki cost

$f_{1} = 3$ GHz par ek core $P_{1} = 15$ W switching power use karta hai. Isse $f_{2} = 4$ GHz par overclock kiya jaata hai voltage unchanged rakhte hue. Naya power?

Forecast: power $f$ mein linear hai — compute karne se pehle guess karo.

Yeh mint C tile hai — frequency lever, akele khicha gaya.

Ratio. $\frac{P _{2}}{P _{1}} = \frac{f _{2}}{f _{1}}$ kyunki sirf $f$ badla hai. Yeh step kyun? $f$ pehli power par aata hai, isliye uska ratio power ko directly scale karta hai.
Compute karo. $\frac{4}{3} \approx 1.333$ . Yeh step kyun? Ratio ko numerically evaluate karte hain taaki agla step plain multiplication ho; 1 se zyaada result already bata deta hai ki power badhegi.
Scale karo. $P_{2} = 1.333 \times 15 = 20$ W. Yeh step kyun? Ratio ko known $P_{1}$ se multiply karne par relative change absolute watts mein wapas aata hai.

Verify karo: $\frac{4}{3} \times 15 = 20$ exactly ✓. Trap note karo: real overclocking aksar $V_{dd}$ bhi badhata hai, isliye actual power linearly se zyaada tezi se badhta hai (Cell I dekho).

Cell D — Activity factor extremes

Worked example D1:

$α = 0$ aur $α = 1$ Ek node mein $C = 8$ pF, $V_{dd} = 1.2$ V, $f = 1$ GHz hai. Uski leakage $I_{leak} = 2$ nA bhi hai. Total power nikalo jab (i) $α = 0$ (idle, kabhi flip nahi karta) aur (ii) $α = 1$ (har cycle flip karta hai).

Forecast: jab $α = 0$ , kya power exactly zero hogi?

Yeh butter D tile hai — activity lever dono extremes par push kiya gaya.

$α = 0$ par Switching. $P_{sw} = 0 \times C V_{dd}^{2} f = 0$ W. Yeh step kyun? Koi flip nahi ⇒ koi charge move nahi ⇒ koi switching energy nahi. Yeh degenerate input hai.
Leakage kabhi nahi soti. $P_{static} = V_{dd} I_{leak} = 1.2 \times 2 \times 1 0^{- 9} = 2.4 \times 1 0^{- 9}$ W $= 2.4$ nW. Yeh step kyun? Static power $α$ par depend nahi karta — ek frozen circuit bhi leakage karta hai.
$α = 0$ par Total: $0 + 2.4 nW = 2.4$ nW. Yeh step kyun? Total power dynamic aur static terms ka sum hai; dynamic zero ho jaane par, poora idle draw pure leakage hai — yeh is cell ka headline lesson hai.
$α = 1$ par Switching. $P_{sw} = 1 \times 8 \times 1 0^{- 12} \times (1.2)^{2} \times 1 \times 1 0^{9} = 8 \times 1.44 \times 1 0^{- 3} = 1.152 \times 1 0^{- 2} W .$ Yeh $11.52$ mW hai. Yeh step kyun? $α = 1$ set karna maximum activity case hai, isliye yeh is node ki sabse badi dynamic power hai — step 1 ka opposite extreme.
$α = 1$ par Total: $11.52 mW + 2.4 nW \approx 11.52$ mW (leakage yahan negligible hai). Yeh step kyun? Dono terms add karne se pata chalta hai ki full activity par leakage dynamic ki roughly millionth hai, isliye kisi bhi practical estimate mein woh nikalti hai — step 3 ka mirror image.

Verify karo: $α = 0$ limit par answer zero nahi hai — leakage rehti hai, yahi static power ka point hai ✓. $α = 1$ par dynamic, static se $\sim 1 0^{6} \times$ zyaada hai ✓.

Cell E — Short-circuit term aur uska cutoff

Worked example E1: Kya shoot-through fire karta hai ya nahi?

Parent ke inverter approximation ko use karte hue $P_{sc} \approx \frac{β}{12} (V_{dd} - 2 V_{t h})^{3} τ f,$ do naye symbols aate hain. Plain words mein:

$β$ ::: transistor drive-strength (gain) factor amps per volt² mein — device kitna current push kar sakta hai given gate over-drive ke liye; bade, wide transistors mein bada $β$ hota hai.
$τ$ ::: signal transition time seconds mein — input ko 0 se $V_{dd}$ tak swing karne mein kitna waqt lagta hai (dekho Signal Transition Time). Dono transistors sirf is window mein overlap-conduct karte hain, isliye lamba $τ$ matlab zyaada shoot-through.
$V_{t h}$ ::: threshold voltage — woh gate voltage jo transistor ko on karne ke liye chahiye.

Do designs compare karo. Dono mein $β = 1 \times 1 0^{- 3}$ A/V², $τ = 50$ ps, $f = 1$ GHz, $V_{t h} = 0.35$ V hai. (i) $V_{dd} = 1.0$ V. (ii) $V_{dd} = 0.6$ V.

Forecast: case (ii) mein, kya $V_{dd} - 2 V_{t h}$ positive hai ya negative — aur iska physically kya matlab hai?

Yeh lavender E tile hai — phir ek voltage lever, lekin shoot-through term par hard cutoff ke saath.

Case (i): gap compute karo. $V_{dd} - 2 V_{t h} = 1.0 - 0.70 = 0.30$ V $> 0$ . Yeh step kyun? Shoot-through tabhi hoti hai jab supply dono transistors ko saath on kar sake, jiske liye $V_{dd} > 2 V_{t h}$ chahiye.
Plug in karo. $P_{sc} = \frac{1 0 ^{- 3}}{12} (0.30)^{3} (50 \times 1 0^{- 12}) (1 0^{9}) .$ $(0.30)^{3} = 0.027$ ; $τ f = 50 \times 1 0^{- 12} \times 1 0^{9} = 0.05$ . $P_{sc} = \frac{1 0 ^{- 3}}{12} \times 0.027 \times 0.05 = 1.125 \times 1 0^{- 7} W = 112.5 nW .$ Yeh step kyun? Gap positive confirm hone ke baad formula valid hai, isliye actual shoot-through power pane ke liye base units mein har value substitute karte hain; $τ f$ pehle group karna arithmetic clean rakhta hai.
Case (ii): cutoff. $V_{dd} - 2 V_{t h} = 0.6 - 0.70 = - 0.10$ V $< 0$ . Yeh step kyun? Formula ek negative cube dega — physically impossible. Sahi interpretation yeh hai: dono transistors kabhi simultaneously on nahi hote, isliye $P_{sc} = 0$ hai, negative number nahi.

Verify karo: Case (i) typical switching power ka ek tiny fraction hai ✓. Case (ii) $V_{dd} < 2 V_{t h}$ degenerate case hit karta hai: zero par clamp karo ✓. Voltage girane se shoot-through khatam hoti hai — yeh low-voltage design ke clean hone ki ek wajah hai.

Cell F — Static vs dynamic crossover

Worked example F1: Leakage kab bhaari padti hai?

Ek block: $C = 20$ pF, $V_{dd} = 0.9$ V, $f = 2$ GHz, leakage $I_{leak} = 5$ mA (ek bada, garam modern node). Woh activity factor $α^{*}$ nikalo jis par dynamic power static power ke barabar ho jaati hai.

Forecast: kya crossover $α$ tiny hoga ya 1 ke paas?

Yeh coral F tile hai — ek ratio/balance question jo dynamic ko leakage se tartol karta hai.

Dono ko barabar set karo. $α^{*} C V_{dd}^{2} f = V_{dd} I_{leak} .$ Yeh step kyun? "Crossover" ka literally matlab hai dono terms barabar hain; unknown $α$ ke liye solve karo.
$α^{*}$ ke liye solve karo. Ek $V_{dd}$ cancel karo: $α^{*} = \frac{I _{leak}}{C V _{dd} f} .$ Yeh step kyun? Dono sides mein $V_{dd}$ factor hai, isliye use cancel karne se unknown $α^{*}$ sabse kam terms ke saath isolate hota hai — arithmetic se pehle algebra numbers ko chota rakhti hai.
Plug in karo. $α^{*} = \frac{5 \times 1 0 ^{- 3}}{( 20 \times 1 0 ^{- 12} ) ( 0.9 ) ( 2 \times 1 0 ^{9} )} .$ Denominator $= 20 \times 1 0^{- 12} \times 0.9 \times 2 \times 1 0^{9} = 3.6 \times 1 0^{- 2}$ . $α^{*} = \frac{5 \times 1 0 ^{- 3}}{3.6 \times 1 0 ^{- 2}} = 0.1389.$ Yeh step kyun? Isolated formula mein base-unit values substitute karne se symbolic crossover condition ek concrete activity threshold banti hai jise hum real workloads se compare kar sakte hain.

Verify karo: Kisi bhi $α < 0.139$ ke liye chip leakage-dominated hai — real idle CPUs yahan hote hain, isliye Power Gating Techniques poore blocks ka $V_{dd}$ cut karta hai. $α^{*}$ $[0, 1]$ mein ek valid fraction hai ✓.

Cell G — Real-world word problem

Worked example G1: Power budget se battery life

Ek wearable SoC average $P_{total} = 50$ mW use karta hai. Battery mein $E = 1.5$ watt-hours (Wh) energy hai. Woh kitne ghante chalega? Phir: Dynamic Voltage Frequency Scaling (DVFS) $V_{dd}$ ko 1.0 V se 0.8 V par laata hai. 50 mW is tarah split hai: 40 mW dynamic + 10 mW static. Naya runtime kya hai?

Forecast: 20% voltage cut — kya runtime 20% se zyaada badhega ya kam?

Yeh mint G tile hai — real-world word problem jo watts ko hours mein translate karta hai.

Baseline runtime. $t = E / P = 1.5 Wh /0.050 W = 30$ hours. Yeh step kyun? Energy ÷ power = time; watt-hours ÷ watts = hours directly.
Power split karo. Dynamic $= 40$ mW; static $= 10$ mW. Yeh step kyun? Dono terms voltage ke saath alag tarike se scale hote hain, isliye hum unhe alag track karna chahte hain — yeh exactly woh correction hai jo reviewer ne maangi thi.
Dynamic scale karo — quadratic. $(\frac{0.8}{1.0})^{2} = 0.64$ , isliye naya dynamic $= 0.64 \times 40 = 25.6$ mW. Yeh step kyun? $P_{dynamic} \propto V_{dd}^{2}$ .
Static scale karo — linear. Kyunki $P_{static} = V_{dd} I_{leak}$ aur $I_{leak}$ (first order tak) fixed hai, static linearly $V_{dd}$ ke saath scale karta hai: factor $\frac{0.8}{1.0} = 0.8$ , isliye naya static $= 0.8 \times 10 = 8$ mW. Yeh step kyun? Static constant rakhna $P_{static} = V_{dd} I_{leak}$ se contradict karta; formula demand karta hai ki yeh $V_{dd}$ ke saath gire. (Real leakage current bhi voltage ke saath girta hai, isliye yeh ek conservative estimate hai.)
Naya total aur runtime. $P^{'} = 25.6 + 8 = 33.6$ mW; $t^{'} = 1.5/0.0336 = 44.64$ hours. Yeh step kyun? Runtime combined draw par depend karta hai, isliye energy ko power se divide karne se pehle alag-alag scaled dono terms ko wapas add karna zaroori hai — sirf ek term scale karna galat battery life deta.

Verify karo: Runtime 30 h se $\approx 44.6$ h ho gaya, 20% voltage cut se $\approx 49%$ gain — quadratic dynamic term savings mein dominate karta hai ✓. Units: Wh/W = h ✓.

Cell H — Static power ki linear voltage scaling

Worked example H1: Leakage sirf linearly girti hai

Ek dark (idle) chip block $I_{leak} = 4$ mA leak karta hai, jo essentially small voltage changes se independent hai. Yeh $V_{1} = 1.0$ V par chalta hai. Uski static power compute karo, phir $V_{2} = 0.7$ V par girane ke baad static power. Fractional drop ko compare karo us se jo ek dynamic term deta.

Forecast: 30% voltage cut — kya leakage power 30% girti hai ya zyaada (jaisa dynamic girata)?

Yeh butter H tile hai — leakage lever, uska linear voltage law dikhata hai.

1.0 V par Static. $P_{static, 1} = V_{1} I_{leak} = 1.0 \times 4 \times 1 0^{- 3} = 4 \times 1 0^{- 3}$ W $= 4$ mW. Yeh step kyun? $P_{static} = V_{dd} I_{leak}$ ka direct application — leakage mein koi $α$ , $C$ , ya $f$ nahi hota.
0.7 V par Static. $P_{static, 2} = 0.7 \times 4 \times 1 0^{- 3} = 2.8 \times 1 0^{- 3}$ W $= 2.8$ mW. Yeh step kyun? Sirf $V_{dd}$ badla aur yeh pehli power par aata hai, isliye ratio $\frac{0.7}{1.0} = 0.7$ hai — plain linear scaling.
Dynamic se compare karo. Usi cut par ek dynamic term $0. 7^{2} = 0.49$ se scale hota. Static $0.7$ se scale hua. Yeh step kyun? Key edge case highlight karta hai: leakage $V_{dd}$ mein linear hai, isliye voltage scaling static power ko dynamic power se kam help karta hai.

Verify karo: Static $1 - 0.7 = 30%$ gira — exactly voltage cut, linear (quadratic nahi) dependence confirm karta hai ✓. Dynamic $51%$ gira hota. Isliye jo chips zyaada idle rehte hain woh Power Gating Techniques (jo $I_{leak}$ zero kar deta hai) par lean karte hain, sirf voltage par nahi.

Cell I — Exam twist

Worked example I1: DVFS voltage AUR frequency saath scale karta hai

Ek core $V_{1} = 1.0$ V, $f_{1} = 3$ GHz par $P_{1} = 12$ W dynamic power use karta hai. Energy bachane ke liye, DVFS isse $V_{2} = 0.8$ V par le jaata hai aur, timing valid rakhne ke liye, frequency bhi $f_{2} = 2.1$ GHz par girata hai. Naya dynamic power nikalo.

Forecast: do cuts multiplicatively stack hote hain — guess karo ki power half se zyaada girti hai ya nahi.

Yeh lavender I tile hai — exam twist, voltage aur frequency dono levers saath kheechta hai.

Combined ratio. Sirf $V$ aur $f$ badle hain: $\frac{P _{2}}{P _{1}} = (\frac{V _{2}}{V _{1}})^{2} \cdot \frac{f _{2}}{f _{1}} .$ Yeh step kyun? $α, C$ constant hain; formula ka $V^{2} f$ factor exactly bata deta hai ki ratios ko kis power par raise karna hai.
Voltage part. $(\frac{0.8}{1.0})^{2} = 0.64$ . Yeh step kyun? Har lever ka ratio alag evaluate karte hain taaki combine karne se pehle total drop mein unke contributions visible hon.
Frequency part. $\frac{2.1}{3.0} = 0.70$ . Yeh step kyun? Frequency linear hai, isliye uska ratio pehli power par aata hai — akele compute karne se pata chalta hai ki clock se kitni saving aati hai versus voltage se.
Multiply karo. $0.64 \times 0.70 = 0.448$ . Yeh step kyun? Independent scaling factors multiply hote hain, isliye combined effect product hai — yahi wajah hai ki do DVFS levers couple karne se dono akele se zyaada bachata hai.
Scale karo. $P_{2} = 0.448 \times 12 = 5.376$ W. Yeh step kyun? Combined ratio ko known $P_{1}$ se multiply karna fractional drop ko absolute watts mein wapas convert karta hai.

Verify karo: Power original ka lagbhag 45% raha — modest cuts se half se zyaada bacha, kyunki dono effects compound hote hain ✓. Isliye DVFS voltage aur frequency dono reductions pair karta hai, koi ek akele nahi.

Worked example I2: Formula invert karo — capacitance ke liye solve karo

Ek engineer ek net par $P_{switching} = 7.2$ mW measure karta hai, $α = 0.3$ , $V_{dd} = 1.2$ V, $f = 2.5$ GHz par. Yeh kaun sa load capacitance $C$ imply karta hai?

Forecast: picofarad-scale answer expect karo.

Rearrange karo. $P = α C V_{dd}^{2} f$ se, $C = \frac{P}{α V _{dd}^{2} f} .$ Yeh step kyun? Hum $C$ chhod kar sab jaante hain; algebra use isolate karta hai.
Plug in karo. $C = \frac{7.2 \times 1 0 ^{- 3}}{0.3 \times ( 1.2 ) ^{2} \times 2.5 \times 1 0 ^{9}} .$ Denominator $= 0.3 \times 1.44 \times 2.5 \times 1 0^{9} = 1.08 \times 1 0^{9}$ . $C = \frac{7.2 \times 1 0 ^{- 3}}{1.08 \times 1 0 ^{9}} = 6.667 \times 1 0^{- 12} F = 6.67 pF .$ Yeh step kyun? Inverted formula mein measured numbers substitute karne se ek observed power woh physical capacitance banti hai jisne use produce kiya.

Verify karo: Answer picofarads mein hai ✓, Capacitance in VLSI se real net capacitance se match karta hai. Back-substitute karo: $0.3 \times 6.667 p \times 1.44 \times 2.5 G = 7.2$ mW ✓.

Recall Self-check

Agar activity factor 0 hai, toh kya total power zero hai? ::: Nahi — dynamic power zero hai lekin static (leakage) power rehti hai. 20% voltage cut se switching power kitna kam hoti hai? ::: Lagbhag 36% (factor $0. 8^{2} = 0.64$ ). 30% voltage cut se static power kitna kam hoti hai? ::: Exactly 30% — static $V_{dd}$ mein linear hai. Short-circuit power exactly zero kab hoti hai? ::: Jab $V_{dd} < 2 V_{t h}$ ; formula ko 0 par clamp karo, kabhi negative nahi.

Yeh bhi dekho: CMOS Inverter Design · Thermal Design Power (TDP) · FinFET Transistors · Subthreshold Slope · Signal Transition Time · Amdahl's Law