Synchronous vs asynchronous counters: Worked examples

The parent note told you what ripple and synchronous counters are. This child page exercises every corner of the maths: every frequency-division case, every settle-time case, the degenerate one-bit counter, the limiting large- $n$ behaviour, a real-world word problem, and an exam-style trap.

Before we start, here is every symbol and tool we will use, and what each means in plain words — because we reuse them relentlessly.

Definition Symbols on this page (all earned in the parent)

$f$ = the clock frequency: how many clock edges arrive per second (in Hz = edges/second).
$Q_{k}$ = the output line of flip-flop number $k$ : a single wire that is either 0 (low) or 1 (high). $Q_{0}$ is the least-significant bit (LSB), and reading $Q_{n - 1} \dots Q_{1} Q_{0}$ as binary gives the counter's number.
$t_{p d}$ = propagation delay of one flip-flop: the wait between a clock edge and the output finally settling (see Propagation delay).
$t_{AND}$ = delay of the AND gate(s) that compute a synchronous flip-flop's toggle condition; $t_{setup}$ = the small time a flip-flop input must be steady before the edge.
ratio = the plain division factor we want, defined as $ratio = \frac{f _{in}}{f _{out}}$ — literally "input frequency divided by desired output frequency." It tells us how many times we must halve.

The scenario matrix

Every problem this topic can throw is one of these cells. The worked examples below are labelled [Cell X] so you can see the whole space is covered.

Cell	Case class	What makes it tricky
A	Exact power-of-2 division	clean $2^{n}$ , count $n$
B	Non-power-of-2 target	must round FF count up, output not exact
C	Degenerate: $n = 1$	one flip-flop — is it even a "counter"?
D	Ripple settle-time	delays add; find $f_{m a x}$
E	Sync settle-time + compare	delay independent of $n$ ; speed-up ratio
F	Limiting large- $n$	what happens to $f_{m a x}$ as $n \to \infty$
G	Word problem	pick components from a real spec
H	Exam twist: toggle logic	$T_{k} = \prod Q_{i}$ vs $T_{k} = Q_{k - 1}$ trap

Case A — exact power-of-2 division

Case B — the target is NOT a power of two

Worked example Ex 2 — Divide 10 MHz down to "about 1 MHz"

[Cell B] Forecast: the ratio is 10, which is not a power of two. Will 3 stages or 4 stages get closer to 1 MHz?

Step 1 — ratio. Why this step? Same first move — measure how much division we want, $ratio = f_{in} / f_{out}$ . $ratio = \frac{10}{1} = 10$

Step 2 — trap the ratio between powers of two. Why this step? A pure ripple counter can only divide by exact powers of two, so we must see which powers bracket 10. $2^{3} = 8 < 10 < 16 = 2^{4}$

Step 3 — pick and report the actual output. Why this step? We cannot hit 1 MHz exactly with a plain $\div 2^{n}$ counter, so we honestly compute what each choice gives. $3 FF : \frac{10}{8} = 1.25 MHz, 4 FF : \frac{10}{16} = 0.625 MHz$ $1.25$ MHz is $0.25$ off; $0.625$ MHz is $0.375$ off. 3 flip-flops is closer.

Verify: $10/8 = 1.25$ and $∣1.25 - 1∣ = 0.25 < ∣0.625 - 1∣ = 0.375$ ✔.

Case C — the degenerate one-flip-flop counter

Worked example Ex 3 — Is a single T flip-flop a counter?

[Cell C] Forecast: with $n = 1$ , $t_{settle} = 1 \cdot t_{p d}$ . Does "ripple vs synchronous" even mean anything here?

Step 1 — apply the ripple formula at $n = 1$ . Why this step? We must check the edge of the domain — formulas must survive their smallest input. $t_{settle} = n t_{p d} = 1 \cdot t_{p d} = t_{p d} \Rightarrow f_{m a x}^{ripple} = \frac{1}{t _{p d}}$

Step 2 — set $t_{AND} = 0$ in the sync formula, and say why. Why this step? With only one flip-flop there is no lower bit to AND, so there is no AND gate at all — its delay is literally zero. Also there is no cascaded clock, so we drop $t_{setup}$ of the (absent) upper stage. Substituting $t_{AND} = 0$ : $f_{m a x}^{sync}_{t_{AND} = 0} = \frac{1}{t _{p d} + 0} = \frac{1}{t _{p d}} = f_{m a x}^{ripple}$ The two families give the identical number.

Step 3 — interpret. Why this step? Numbers alone can mislead; we ask what it means. With one flip-flop there is no second clock to cascade, so "ripple" and "synchronous" are identical — the distinction only appears once $n \geq 2$ . A lone T flip-flop just does ÷2. It counts the single sequence $0, 1, 0, 1, \dots$ — technically a modulo-2 counter.

Verify: at $n = 1$ with $t_{AND} = 0$ , ripple and sync max frequencies both equal $1/ t_{p d}$ ✔.

Case D — ripple settle time

Case E — synchronous, and the speed-up ratio

Case F — the limiting behaviour as $n$ grows

Worked example Ex 6 — What happens as

$n \to \infty$ ? [Cell F] Forecast: which family survives large $n$ , and which collapses?

Step 1 — take the limit for ripple. Why this step? We want the trend, not one number, so we see how each formula behaves as $n$ blows up. $lim_{n \to \infty} f_{m a x}^{ripple} = lim_{n \to \infty} \frac{1}{n t _{p d}} = 0$ A huge ripple counter's max clock tends to zero — it gets uselessly slow.

Step 2 — take the limit for sync (idealised tree). Why this step? Compare directly, holding $t_{AND}$ fixed. $lim_{n \to \infty} f_{m a x}^{sync} = \frac{1}{t _{p d} + t _{AND} + t _{setup}} = constant$ It doesn't depend on $n$ , so it stays flat. Look at s03: the red ripple curve dives toward the axis, the green sync line is horizontal.

Step 3 — unpack the "ideal tree" caveat. Why this step? That flat line assumed $t_{AND}$ stays constant, but in real silicon it does not — and a good engineer must know why. A synchronous bit $k$ ANDs together all $k$ lower bits. As $n$ grows, that AND gate has more inputs (its fan-in grows), and wide gates are slower, so $t_{AND}$ creeps up — mildly (like $lo g n$ for a balanced tree of small AND gates), not linearly like ripple. Carry-lookahead structuring keeps this growth gentle; that is precisely why we say "ideal tree." Bottom line: sync still crushes ripple for large $n$ , just not perfectly flat.

Verify (spot values, $t_{p d} = 8$ ns): ripple at $n = 2, 10, 100$ gives $62.5, 12.5, 1.25$ MHz — strictly falling toward 0 ✔; sync stays $\approx 83.3$ MHz for all three ✔.

Case G — real-world word problem

Case H — exam twist: the toggle-logic trap

Worked example Ex 8 — Give

$T_{4}$ for a synchronous up-counter, then say when bit 4 flips [Cell H] Forecast: is it $T_{4} = Q_{3}$ , or something bigger?

Step 1 — recall the carry condition. Why this step? In binary counting, a digit increments only when a carry reaches it — meaning every lower digit is 1, not just the neighbour. (Recall $Q_{i}$ is the output wire of flip-flop $i$ , value 0 or 1.) $T_{4} = Q_{0} Q_{1} Q_{2} Q_{3} = \prod_{i = 0}^{3} Q_{i}$

Step 2 — find the exact transition. Why this step? "When does bit 4 flip?" = when all four lower bits are 1, i.e. state $\dots 01111$ . $Q_{3} Q_{2} Q_{1} Q_{0} = 111 1_{2} = 15 \Rightarrow on the next edge 15 \to 16 bit 4 turns on$

Step 3 — expose the trap. Why this step? The seductive wrong answer is $T_{4} = Q_{3}$ (copying ripple's "clocked by previous bit"). But in synchronous design all flip-flops share the clock, so each must self-decide by AND-ing all lower bits.

Verify: $T_{4}$ is 1 only in state $0 \dots 01111$ ; at $15$ , $Q_{0} = Q_{1} = Q_{2} = Q_{3} = 1$ so the product is $1$ ; at any state below 15 at least one lower bit is 0 so the product is $0$ ✔. And $1 5_{10} = 111 1_{2}$ , $1 6_{10} = 1000 0_{2}$ ✔.

Recall Rapid self-check across the matrix

Divide 16 MHz → 1 MHz needs how many FF? ::: 4 (since $2^{4} = 16$ ). Closest ripple stage count for 10→1 MHz? ::: 3 FF, giving 1.25 MHz. 6-bit ripple, $t_{p d} = 8$ ns, $f_{m a x}$ ? ::: about 20.83 MHz. Same 6-bit synchronous with 12 ns total, $f_{m a x}$ ? ::: about 83.3 MHz (4× faster). As $n \to \infty$ , ripple $f_{m a x}$ tends to? ::: 0 (it collapses); sync stays ~constant (mild $t_{AND}$ growth). A 32768 Hz crystal needs how many FF for a 1 Hz tick? ::: 15 (since $2^{15} = 32768$ ). Synchronous $T_{4}$ equals? ::: $Q_{0} Q_{1} Q_{2} Q_{3}$ , flips at $15 \to 16$ .

Connections

Frequency division — every ÷ $2^{n}$ example above
Propagation delay — the $t_{p d}$ that adds in ripple
Modulo-N counters — how to divide by a non-power-of-two (Cell B)
Carry lookahead — the AND-tree keeping sync speed near-flat (Cells E, F)
T flip-flop / JK flip-flop — the toggling unit in every example
Clock skew — the real-world caveat behind "all clocks fire together"