Synchronous vs asynchronous counters: Foundations — Hardware deep dive

Before you can read the parent note Synchronous vs asynchronous counters, you need every symbol it silently assumes. We build each one from nothing: plain words → a picture → why the topic needs it.

1. A binary digit (bit): 0 and 1

Why start here? Because a counter counts in binary. If you don't know what a single 0/1 wire means, nothing above it makes sense.

Look at the figure: one wire, two possible heights. That's the whole alphabet of digital hardware — no in-between values allowed.

2. Binary numbers and place value: reading $Q_{2} Q_{1} Q_{0}$

Several bits side by side make a number. The parent writes states like $Q_{2} Q_{1} Q_{0}$ . What does that mean?

The subscript in $Q_{0}, Q_{1}, Q_{2}$ is just a name tag saying which column that bit lives in:

$Q_{0}$ = rightmost = the least significant bit (LSB), worth $1$ .
The highest subscript = leftmost = the most significant bit (MSB).

Why the topic needs this: "counting up" is adding 1 in binary, and a carry rippling from LSB toward MSB is the entire reason ripple counters ripple.

3. Counting = adding 1, and the carry

Watch what happens as we count $0, 1, 2, 3, 4$ in 3-bit binary:

$000 \to 001 \to 010 \to 011 \to 100$

4. The overline: $\overline{Q}$ (NOT)

The parent writes $\overline{Q_{k - 1}}$ . The bar means NOT — flip the value.

Why needed: some ripple counters clock the next stage from $\overline{Q}$ instead of $Q$ (it decides whether the counter counts up or down). You must recognise the bar before you meet it.

5. AND, and the product notation $\prod$

The multiplication dot is not ordinary arithmetic here — for single bits, "AND" and "multiply" happen to give the same table ( $1 \cdot 1 = 1$ , everything else $0$ ), which is why hardware people write it as a product.

Why needed: this is exactly the carry rule from §3. "Bit $k$ flips when all lower bits are 1" = "AND of all lower bits = 1" = $\prod_{i = 0}^{k - 1} Q_{i}$ . The notation and the physical carry are the same idea.

6. A flip-flop: the memory that flips

The counter is a chain of flip-flops, so this is the atom of the whole topic. Two kinds appear:

T flip-flop — has one control input $T$ . If $T = 1$ it toggles (flips) on each clock edge; if $T = 0$ it holds.
JK flip-flop — a more general flip-flop; setting $J = K = 1$ makes it behave exactly like a T with $T = 1$ .

7. The clock and the "edge"

Why needed: the entire sync-vs-async distinction is "which wire delivers each flip-flop's clock edge." Same shared beat = synchronous; each flip-flop poked by the previous one's output = asynchronous. You cannot understand that sentence without knowing what an edge is.

8. Frequency $f$ and dividing by two

Chain $n$ flip-flops and each halves again, giving $f /2, f /4, f /8, \dots$ — that is Frequency division and it's why a ripple counter of $n$ flip-flops divides by $2^{n}$ . See Modulo-N counters for stopping early at a non-power-of-2.

9. Propagation delay $t_{p d}$

Why needed: in a ripple counter these delays stack (each stage waits for the last), giving total delay $n \cdot t_{p d}$ — the parent's reason ripple counters are slow. See Propagation delay and its cousin Clock skew (clock edges arriving at slightly different times). The Carry lookahead trick fights this by pre-computing all carries in parallel.

Prerequisite map

Equipment checklist

Read

011

as a decimal number

0 \cdot 4 + 1 \cdot 2 + 1 \cdot 1 = 3

Which bit is

Q_{0}

and what is it worth?

The least significant bit (rightmost), worth

2^{0} = 1

What does the bar in

\overline{Q}

do?

NOT — turns 1 into 0 and 0 into 1.

When does bit

k

flip while counting up?

When every lower bit is already 1 (a carry rolls up into it).

What does

\prod_{i = 0}^{k - 1} Q_{i}

mean?

AND all the lower bits together:

Q_{0} \cdot Q_{1} \dots Q_{k - 1}

What is a flip-flop?

A one-bit memory that only changes on a clock edge.

What is a clock edge?

The instant the clock switches — rising (

0 \to 1

) or falling (

1 \to 0

Why does a T flip-flop with

T = 1

halve the frequency?

One output cycle needs two toggles, and each toggle needs one clock edge.

What is

t_{p d}

Propagation delay — the small time an output takes to settle after a clock edge.

Why does ripple delay grow with

n

Each stage waits for the previous one, so delays add:

n \cdot t_{p d}

Connections

T flip-flop · JK flip-flop — the toggling atom
Propagation delay · Clock skew — timing limits
Frequency division — the $\div 2^{n}$ behaviour
Carry lookahead — parallel carry to beat ripple delay
Modulo-N counters — counting to non-powers of 2