Synchronous vs asynchronous counters: Exercises — Hardware deep dive

This page is a self-testing ladder. Every problem sits inside a level (L1 easiest → L5 hardest), and every solution is hidden inside a collapsible callout so you can try first, then reveal. Nothing here uses a symbol the parent note didn't build — but let us re-anchor the three tools you will lean on so line one makes sense.

Definition The three quantities we reuse everywhere

$f$ = clock frequency = how many clock edges arrive per second (unit: Hz = "per second"). Picture a metronome ticking.
$t_{p d}$ = propagation delay = the small time gap between a clock edge arriving at a flip-flop and its output $Q$ finishing its change. Picture a light switch that takes a moment to actually turn the bulb on. See Propagation delay.
$Q_{k}$ = the output bit of flip-flop number $k$ , where $k = 0$ is the LSB (least-significant / rightmost / fastest-changing bit). Reading $\dots Q_{2} Q_{1} Q_{0}$ left-to-right gives you a binary number.

Two rules from the parent that we treat as facts:

one T flip-flop with $T = 1$ halves the frequency of whatever clock it sees: $f_{out} = f_{clk} /2$ ;
a ripple counter's settle time adds up ( $n \cdot t_{p d}$ ), a synchronous one does not ( $\approx t_{p d} + t_{AND}$ ).

Everything below is just those facts, pushed harder.

Level 1 — Recognition

Can you read the wiring and name what you see?

Recall Solution L1·1

Clock wiring is the whole test. Here each later flip-flop is clocked by the previous output, not by a shared master clock. That is the definition of an asynchronous (ripple) counter. The bits update one after another — they ripple from LSB to MSB.

Recall Solution L1·2

$T_{0} = 1$ , constant. The LSB flips on every clock edge — that is what makes it the fastest, half-frequency bit. There is no lower bit to gate it, so nothing can ever stop it toggling.

Level 2 — Application

Plug numbers into the parent's formulas.

Recall Solution L2·1

Each flip-flop divides by 2, and $n$ of them divide by $2^{n}$ . We need $2^{n} = 32$ , so $n = 5$ (since $2^{5} = 32$ ). The last flip-flop $Q_{4}$ runs at $f / 2^{5} = f /32$ . See Frequency division.

Recall Solution L2·2

Delays add in series: $t_{settle} = n \cdot t_{p d} = 6 \times 8 = 48 ns$ . Maximum frequency is one count per settle window: $f_{m a x} = 1/48 ns \approx 20.8 MHz$ . Any faster and the LSB starts a new count before the MSB finished the old one — the number is never valid.

Recall Solution L2·3

Synchronous delay does not scale with $n$ : $t = t_{p d} + t_{AND} = 8 + 4 = 12 ns$ , so $f_{m a x} = 1/12 ns \approx 83.3 MHz$ . Speed-up $= 48/12 = 4 \times$ . The bigger the counter, the bigger this gap grows — that is why wide counters go synchronous.

Level 3 — Analysis

Trace real behaviour, including the glitches.

Figure — Synchronous vs asynchronous counters

Recall Solution L3·1

Going $7 \to 8$ means bits 0,1,2 must clear and bit 3 must set — but they do it in sequence, LSB first.

$t = 0$ : clock edge arrives at FF0. State still $0111$ .
$t = 5 ns$ : $Q_{0} : 1 \to 0$ . Its fall clocks FF1. State $0110$ (decimal 6) — wrong.
$t = 10 ns$ : $Q_{1} : 1 \to 0$ . Its fall clocks FF2. State $0100$ (decimal 4) — wrong.
$t = 15 ns$ : $Q_{2} : 1 \to 0$ . Its fall clocks FF3. State $0000$ (decimal 0) — wrong.
$t = 20 ns$ : $Q_{3} : 0 \to 1$ . State $1000$ (decimal 8) — correct at last.

The counter briefly displayed $6, 4, 0$ — three decoding glitches — and only settled after $4 \times 5 = 20 ns$ . These are real states, not bugs.

Recall Solution L3·2

With $Q_{0} = Q_{1} = Q_{2} = 1, Q_{3} = 0$ :

$T_{0} = 1$ (always).
$T_{1} = Q_{0} = 1$ .
$T_{2} = Q_{0} Q_{1} = 1$ .
$T_{3} = Q_{0} Q_{1} Q_{2} = 1$ . All four T-inputs are 1, so on the shared clock edge all four bits toggle at once: $0111 \to 1000$ . Because they move together, no intermediate wrong value ever appears — contrast L3·1.

Recall Solution L3·3

Bit 3 must flip only on a full carry out of the low three bits, i.e. exactly when they read $111$ . If we wrongly used $T_{3} = Q_{2}$ , bit 3 would try to toggle every time $Q_{2} = 1$ — that includes states like $0100$ (decimal 4), where no carry into bit 3 is happening. The AND of all lower bits is precisely the binary carry condition. See Carry lookahead.

Level 4 — Synthesis

Design something new by combining the pieces.

Recall Solution L4·1

We need a division ratio $48/1.5 = 32 = 2^{5}$ , so 5 flip-flops. Intermediate frequencies (each halves the previous): $Q_{0} : 24, Q_{1} : 12, Q_{2} : 6, Q_{3} : 3, Q_{4} : 1.5 (all MHz) .$ The final output $Q_{4}$ is the wanted $1.5 MHz$ .

Recall Solution L4·2

Clock period demanded: $1/40 MHz = 25 ns$ per edge.

Ripple settle: $8 \times 6 = 48 ns > 25 ns$ → fails (needs $f_{m a x} = 1/48 ns \approx 20.8 MHz$ ).
Synchronous settle: $6 + 3 = 9 ns < 25 ns$ → passes ( $f_{m a x} = 1/9 ns \approx 111 MHz$ ).

Only the synchronous counter meets $40 MHz$ . This is the classic width-vs-speed trade forced by the $n t_{p d}$ term.

Recall Solution L4·3

To represent up to decimal 9 you need enough bits so that $2^{n} > 9$ : $n = 4$ gives $2^{4} = 16 \geq 10$ . So 4 flip-flops. A natural 4-bit counter would run $0 \to 15$ ; to stop at 9 we detect the first illegal state, decimal $10 = 1010$ , and use it to reset all flip-flops back to $0000$ . See Modulo-N counters. This is a "reset-on-N" design.

Level 5 — Mastery

Reason at the edge: skew, degenerate cases, limits.

Recall Solution L5·1

This is clock skew — the same edge reaching different flip-flops at slightly different times (see Clock skew). Small skew is harmless. But if $Δ$ approaches a flip-flop's $t_{p d}$ , an early flip-flop's new output can reach a late flip-flop before that late flip-flop has latched its old value — the counter can capture the wrong bit, exactly the kind of race a synchronous design was meant to avoid. So "synchronous" is an ideal; real chips fight skew to stay near it.

Recall Solution L5·2

Ripple: $f_{m a x}^{ripple} (n) = \frac{1}{n t}$ . As $n \to \infty$ , this $\to 0$ — a very wide ripple counter is hopelessly slow.
Sync (ideal / carry-lookahead): $f_{m a x}^{sync} = \frac{1}{t + g}$ , with no $n$ in it — it stays flat regardless of width.

So the ratio $\frac{f _{sync}}{f _{ripple}} = \frac{n t}{t + g}$ grows linearly in $n$ : the wider the counter, the more decisively synchronous wins.

Recall Solution L5·3

Ripple: $f_{m a x} = 1/ (1 \cdot t) = 1/ t$ . Synchronous: $f_{m a x} = 1/ (t + g)$ . With one flip-flop there is no lower bit to AND, so $T_{0} = 1$ needs no gate → $g = 0$ → both give $1/ t$ . Physically a single toggling flip-flop is neither "chained" nor "shared-clocked" — the two families only become distinguishable from two or more flip-flops onward. This is the boundary case where the whole distinction collapses.

Recall Solution L5·4

The transition $2^{m} - 1 \to 2^{m}$ forces $m$ low bits to clear and bit $m$ to set, all in sequence. Each of the $m + 1$ toggles happens one $t_{p d}$ apart. The intermediate states (after each toggle except the last correct one) are the glitches: there are $m$ of them, and the valid value arrives after $(m + 1) t_{p d}$ . For $0111 \to 1000$ : $m = 3$ → 3 glitches ( $0110, 0100, 0000$ ), valid after $4 t_{p d}$ — matching the trace in L3·1. ✔

Connections

T flip-flop, JK flip-flop — the toggling cell every exercise is built from
Propagation delay — the $t_{p d}$ in every timing answer
Frequency division — L2·1, L4·1 dividers
Carry lookahead — the AND-tree behind sync speed (L3·3, L5·2)
Modulo-N counters — L4·3 decade counter
Clock skew — the L5·1 real-world limit
Back to parent: 3.4.08 Synchronous vs asynchronous counters (Hinglish)