Synchronous vs asynchronous counters: Visual walkthrough

We only need one word before we start.

We will use falling edges throughout (marked with a red tick in every figure).

Step 1 — One flip-flop halves the frequency

WHAT. Take a single T flip-flop and wire its $T$ input permanently to $1$ . The rule of such a flip-flop is dead simple: on each clock edge, flip my output $Q$ to the opposite of what it was. That's all "toggle" means — swap $0 \leftrightarrow 1$ .

WHY. Everything a counter does is built from this one behaviour. If we understand exactly what one toggling flip-flop produces, chaining them is just repetition. So we start at the atom.

PICTURE. Look at the figure. The black wave on top is the clock. Each red tick is a falling edge. Below it, $Q$ (the red step wave) flips at every red tick.

Figure — Synchronous vs asynchronous counters

Count the ticks needed for $Q$ to go all the way $0 \to 1 \to 0$ (one full cycle): it takes two ticks. Two input edges per one output cycle means the output wave is stretched to twice the width — half the frequency.

Step 2 — Chain them: the bits become a binary number

WHAT. Now take that halved output $Q_{0}$ and use it as the clock of a second flip-flop, producing $Q_{1}$ . Feed $Q_{1}$ into a third, producing $Q_{2}$ . This is the ripple wiring: only the first flip-flop touches the master clock; each later one is clocked by its neighbour.

WHY. Because halving twice divides by $4$ , three times by $8$ , and so on. If we read the outputs together as digits $Q_{2} Q_{1} Q_{0}$ , those halvings turn out to be binary counting — that is the magic we want to expose.

PICTURE. The figure stacks four waves: the clock, then $Q_{0}$ , $Q_{1}$ , $Q_{2}$ . Each red-highlighted wave toggles on the falling edge of the wave directly above it.

Read the three lower waves as a column of bits at each moment, top digit = $Q_{2}$ (most significant), bottom = $Q_{0}$ (least significant). Reading left to right you get $000, 001, 010, 011, 100, \dots$ — the numbers $0, 1, 2, 3, 4, \dots$

Step 3 — Zoom in on the delay of ONE flip-flop

WHAT. A real flip-flop cannot flip its output the instant the edge arrives. There is a tiny lag — call it $t_{p d}$ , the Propagation delay — between the edge and the output actually settling to its new value.

WHY. This single lag is the whole reason ripple counters are slow. Before we add lags across many flip-flops, we must see one lag clearly.

PICTURE. The red arrow spans the gap between the clock edge (black tick) and the moment $Q$ has finished changing.

Step 4 — In a ripple counter the delays STACK

WHAT. Trace what happens on one master edge in the ripple chain. FF0 settles after $t_{p d}$ . But FF1 is clocked by $Q_{0}$ — so FF1's edge only arrives after $Q_{0}$ has changed. FF1 therefore settles at $2 t_{p d}$ . FF2 waits for FF1: $3 t_{p d}$ . And so on.

WHY. This is the "falling dominoes" claim made concrete. Each domino cannot fall until the previous one has pushed it — so the last one falls much later.

PICTURE. Four staircases, each shifted one $t_{p d}$ to the right of the one above. The red arrow marks the total lag from the first edge to the last bit settling.

Step 5 — The staggering CREATES wrong numbers (glitches)

WHAT. During that stacking window, the bits change one at a time, so intermediate patterns appear that are neither the old number nor the new one. Take the step $0111 \to 1000$ (seven to eight).

WHY. People assume wrong readings mean broken hardware. They don't — these are real, correct voltages, just seen mid-flip. Understanding them is the reason to prefer synchronous designs.

PICTURE. A timeline of the $0111 \to 1000$ transition. Bit 0 falls first, then bit 1, then bit 2, then bit 3 rises last. The red band marks the moment the display briefly reads $0110$ , $0100$ , $0000$ — none of which is $7$ or $8$ .

Step 6 — Synchronous: one shared clock, all bits flip together

WHAT. Rewire so the master clock goes to every flip-flop's clock input at once. Now there is no domino chain — all outputs settle in parallel, one $t_{p d}$ after the shared edge.

WHY. Parallel delays don't add. The whole counter settles in the time of a single flip-flop, no matter how many there are. That kills both the slowness and the glitches at once.

PICTURE. All clock inputs tied to one vertical red line (the shared clock). Every $Q$ steps at the same red tick.

But if everyone flips on the same edge, each flip-flop must decide for itself whether to flip — it can't wait for a neighbour. That decision is Step 7.

Step 7 — The toggle rule: flip only when all lower bits are 1

WHAT. In binary counting, a digit changes exactly when it receives a carry — and a carry only reaches digit $k$ when every digit below it is already $1$ . So we feed each flip-flop's $T$ input the AND of all lower outputs.

WHY. With a shared clock, "wait for the previous bit" is gone. The carry condition replaces it: each bit computes "should I flip?" from the current values of the bits below it, using AND gates (a small Carry lookahead tree).

PICTURE. Bits $Q_{0}, Q_{1}, Q_{2}$ feed an AND gate whose output (red) is $T_{3}$ . It goes high only at state $0111$ , so $Q_{3}$ flips exactly on the $7 \to 8$ step.

Step 8 — Degenerate & limiting cases

WHAT. The corners that "never happen" — until they do.

WHY. The contract: the reader must never meet a case we skipped.

$n = 1$ (one flip-flop). Ripple and synchronous are identical — there is no neighbour to cascade to and no lower bit to AND. Both settle in $t_{p d}$ , both just halve the frequency. The two families only diverge at $n \geq 2$ .
$n \to \infty$ (very long counters). Ripple: $f_{m a x} = 1/ (n t_{p d}) \to 0$ — it grinds to a halt. Synchronous (carry-lookahead style): $f_{m a x} \approx 1/ (t_{p d} + t_{AND})$ stays roughly constant. This is the whole payoff.
All-ones state $\to$ zero (wrap-around). $111 \dots 1 \to 000 \dots 0$ is the worst glitch case: every bit flips at once in ripple, so the settle window shows the longest string of wrong numbers.
$t_{p d} = 0$ (idealised, impossible). Both counters would be glitch-free and infinitely fast; the whole distinction vanishes. That is why $t_{p d}$ is the villain of this entire story — see Clock skew for the real-world twist where even "shared" clocks arrive at slightly different times.

PICTURE. Side-by-side $n = 1$ (identical waves) and $n = 8$ (ripple's last bit lags far off the page, synchronous's does not).

The one-picture summary

One figure, both counters, same clock. Left: ripple — bits form a staircase, last bit settles at $n t_{p d}$ , red glitch band visible. Right: synchronous — all bits step on one red line, settle at $t_{p d}$ , no glitch.

Recall Feynman: the whole walkthrough in plain words

One flip-flop is a light switch that flips every time you clap. Two claps make one on-off cycle, so it blinks at half your clapping speed — that's frequency halving. Chain switches so each one claps for the next, and reading their lights as digits gives you counting: $0, 1, 2, 3 \dots$

But flipping a switch takes a heartbeat ( $t_{p d}$ ). In the chain, switch two can't clap until switch one has finished flipping, so the last light changes way late — and while the row is mid-flip you see wrong numbers flash by. That's the ripple counter: simple, but slow and flickery, and it gets worse the longer the chain.

Fix: give every switch the same clap from a teacher yelling "NOW." They all flip together, so the whole row settles in one heartbeat regardless of length. The catch — each switch must decide by itself whether to flip, using the rule "flip only if every light to my right is already ON" (that's a carry). More wiring (AND gates), but fast and no flicker. And when there's only one switch, both schemes are the exact same thing.

Recall

Two flip-flops chained (ripple), master edge arrives — when does the second bit settle?

After

2 t_{p d}

; it can't start until the first bit has finished settling.

In the synchronous counter, why doesn't total delay grow with

n

All flip-flops share one clock and settle in parallel — delays are parallel, not in series.

What is

T_{3}

in a synchronous up-counter, and at which count does bit 3 flip?

T_{3} = Q_{0} Q_{1} Q_{2}

; bit 3 flips at

0111 \to 1000

(the

7 \to 8

step).

For

n = 1

, how do ripple and synchronous counters differ?

They don't — one flip-flop has no neighbour and no lower bits, so both are identical (just halve the frequency).

Are the wrong numbers during a ripple transition errors?

No — they are real transient voltages (decoding glitches) caused by staggered

t_{p d}

Connections

T flip-flop · JK flip-flop — the toggling atom of every step
Propagation delay — the $t_{p d}$ that stacks in Step 4
Frequency division — Steps 1–2 as $\div 2^{n}$
Carry lookahead — the AND-tree of Step 7
Modulo-N counters — stopping the count early
Clock skew — why "shared clock" is never perfectly shared