Setup and hold time constraints: Worked examples — Hardware deep dive

This page is a drill hall. The parent note Setup and Hold Time Constraints built the two constraints; here we hit every kind of case they can throw at you — from the friendly ones to the nasty degenerate corners.

Before symbols appear, here is the whole vocabulary in one place (all from the parent):

Definition Symbol glossary (read before the examples)

$T$ — clock period (seconds between two edges). $T_{min}$ — the smallest period that still passes setup — the sum of the max-delay path, so $f_{ma x} = 1/ T_{min}$ . $t_{c q}^{ma x}$ — slowest clock-to-Q delay of the launching flip-flop. $t_{c q}^{min}$ — fastest clock-to-Q delay, also called the contamination delay — "contamination" means the moment the old, stable output first starts to change (gets contaminated) after the edge, i.e. the earliest anything can move. $t_{l o g i c}^{ma x}$ — slowest path through the combinational logic between the flip-flops (see Combinational Logic Delay). $t_{l o g i c}^{min}$ — fastest (shortest) path through that logic — its contamination delay. $t_{s u}$ — setup time — data must be stable this long before the edge. $t_{h}$ — hold time — data must be stable this long after the edge. $t_{s k e w}$ — how much later the capturing clock arrives than the launching clock (positive = capture delayed). $f_{ma x}$ — highest safe clock frequency, $= 1/ T_{min}$ .

The scenario matrix

Everything setup/hold analysis can ask you falls into one of these cells. Each worked example below is tagged with the cell(s) it covers.

#	Cell (case class)	What makes it different	Example
A	Plain setup (find $f_{ma x}$ )	slowest path vs next edge, skew $= 0$	Ex 1
B	Plain hold check	fastest path vs hold window, skew $= 0$	Ex 2
C	Both pass / slack reported	compute positive margins, confirm safe	Ex 3
D	Positive skew (helps setup, hurts hold)	$\pm t_{s k e w}$ on both sides	Ex 4
E	Negative skew (hurts setup, helps hold)	sign flip of skew	Ex 5
F	Zero logic (register-to-register, $t_{l o g i c} = 0$ )	degenerate path — pure flip-flop timing	Ex 6
G	Fixing a hold violation by adding buffers	insert min-delay, re-verify	Ex 7
H	Limiting case ( $t_{h} \to 0$ , and $T \to \infty$ )	what constraints survive	Ex 8
I	Real-world word problem (spec a part)	translate English → inequality	Ex 9
J	Exam twist: skew that breaks a passing circuit	slack sign flips as skew grows	Ex 10

The figure below is the timeline every example lives on — pin it in your mind.

Figure — Setup and hold time constraints

Intuition Figure s01 — how to read the timeline (text description)

The horizontal axis is time, in nanoseconds. Two thick lavender vertical lines mark the two clock edges: the launch edge at $t = 0$ (left) and the capture edge at $t = T$ (right, here $T = 10$ ).

The wide mint/green band in the middle is the safe arrival zone for setup: the new data must land inside it, i.e. before $T - t_{s u}$ .
The butter/yellow strip hugging the right edge is the reserved $t_{s u}$ window — the last slice of the period where nothing may still be arriving.
The coral strip hugging the left edge is the hold "keep-still" window of width $t_{h}$ — right after the launch edge, data must not move yet.
A lavender arrow sweeps left-to-right through the mint band: that is the new data crossing the combinational logic on its journey from FF1's $Q$ to FF2's $D$ . Setup is about landing before the yellow strip; hold is about not moving during the coral strip.

Cell A — plain setup, find max frequency

Worked example Ex 1 (Cell A)

$t_{c q}^{ma x} = 0.7$ ns, $t_{l o g i c}^{ma x} = 2.8$ ns, $t_{s u} = 0.5$ ns, skew $= 0$ . Find $f_{ma x}$ .

Forecast: Guess — will $f_{ma x}$ be above or below $250$ MHz? (Add the delays, invert.)

Step 1 — sum the max-delay path to get $T_{min}$ . Why this step? Setup asks whether the slowest data can still arrive before the next edge, so we use every max delay plus the setup reservation. Their sum is the smallest period that still passes — we call it $T_{min}$ (see glossary). $T_{min} = 0.7 + 2.8 + 0.5 = 4.0 ns$ Step 2 — invert $T_{min}$ to a frequency. Why this step? Frequency and period are reciprocals, $f = 1/ T$ ; the smallest safe period gives the largest safe frequency, so $f_{ma x} = 1/ T_{min}$ . $f_{ma x} = \frac{1}{4.0 ns} = 250 MHz$

Verify: Units: ns $^{- 1} = 1 0^{9}$ s $^{- 1} =$ GHz, so $1/4.0 ns = 0.25 GHz = 250$ MHz. ✓ Your forecast: exactly at the boundary.

Cell B — plain hold check

Cell C — both pass, report slack

Cell D — positive skew (helps setup, hurts hold)

Worked example Ex 4 (Cell D)

Take Ex 3's numbers but add capture-clock skew $t_{s k e w} = + 0.5$ ns. Recompute both slacks.

Forecast: One slack goes up, the other goes down. Predict which.

Step 1 — new setup slack. Why this step? Positive skew delays the capture edge, giving data more time: $S_{se t u p} = T + t_{s k e w} - (\dots)$ . $S_{se t u p} = (5 + 0.5) - 4.1 = 1.4 ns (was 0.9, improved)$ Step 2 — new hold slack. Why this step? The same delayed edge extends the keep-still window, so we subtract skew: $S_{h o l d} = (t_{c q}^{min} + t_{l o g i c}^{min}) - (t_{h} + t_{s k e w})$ . $S_{h o l d} = 0.7 - (0.4 + 0.5) = 0.7 - 0.9 = - 0.2 ns (was + 0.3, now fails)$

Verify: Setup improved by exactly $+ 0.5$ , hold worsened by exactly $- 0.5$ — the skew is a pure trade of one for the other. ✓ This is the Clock Skew and Jitter danger the parent's steel-man warned about.

Cell E — negative skew (hurts setup, helps hold)

Worked example Ex 5 (Cell E)

Same base as Ex 3 but $t_{s k e w} = - 0.7$ ns (capture edge arrives earlier than launch). Recompute both slacks.

Forecast: Now the signs of the effects flip. Guess before computing.

Step 1 — setup slack with negative skew. Why this step? An early capture edge steals time from the data path: $S_{se t u p} = T + t_{s k e w} - 4.1$ , and $t_{s k e w}$ is negative here. $S_{se t u p} = (5 + (- 0.7)) - 4.1 = 4.3 - 4.1 = 0.2 ns (shrank from 0.9)$ Step 2 — hold slack with negative skew. Why this step? $S_{h o l d} = (t_{c q}^{min} + t_{l o g i c}^{min}) - (t_{h} + t_{s k e w})$ ; a negative skew subtracts from the window, making hold easier. $S_{h o l d} = 0.7 - (0.4 + (- 0.7)) = 0.7 - (- 0.3) = 1.0 ns (grew from 0.3)$

Verify: Setup dropped by $0.7$ , hold rose by $0.7$ — mirror image of Ex 4. Both still positive, so still passes, but setup is now the tight one. ✓

Cell F — zero logic (register-to-register)

Worked example Ex 6 (Cell F)

Direct FF→FF: $t_{c q}^{ma x} = 0.5$ , $t_{c q}^{min} = 0.1$ , $t_{s u} = 0.4$ , $t_{h} = 0.3$ ns, $t_{l o g i c}^{ma x} = t_{l o g i c}^{min} = 0$ , skew $= 0$ . Find $f_{ma x}$ and check hold.

Forecast: With zero logic, does hold survive? (Compare $t_{c q}^{min}$ alone to $t_{h}$ .)

Step 1 — setup, get $T_{min}$ . Why this step? Same setup formula with $t_{l o g i c}^{ma x} = 0$ ; the sum is the smallest safe period $T_{min}$ . $T_{min} = 0.5 + 0 + 0.4 = 0.9 ns$ Step 2 — invert $T_{min}$ to a frequency. Why this step? The largest safe frequency is the reciprocal of the smallest safe period, $f_{ma x} = 1/ T_{min}$ (same reason as Ex 1 — we restate it here because the numbers changed). $f_{ma x} = \frac{1}{0.9 ns} \approx 1111 MHz$ Step 3 — hold check. Why this step? Hold rule with $t_{l o g i c}^{min} = 0$ becomes simply $t_{c q}^{min} \geq t_{h}$ . $0.1 + 0 = 0.1 ns \geq 0.3 ns ? \Rightarrow FALSE = HOLD VIOLATION$

Verify: Hold slack $= 0.1 - 0.3 = - 0.2$ ns. Real chips solve this by making $t_{c q}^{min} \geq t_{h}$ inside the flip-flop so direct shift chains are safe. Here the given part fails; you'd need $\geq 0.2$ ns extra delay. ✓ ( $f_{ma x}$ : $1/0.9 = 1.111$ GHz.)

Cell G — fixing a hold violation with buffers

Worked example Ex 7 (Cell G)

Continue Ex 6's hold failure ( $t_{c q}^{min} = 0.1$ , $t_{h} = 0.3$ , $t_{l o g i c}^{min} = 0$ ). Insert a buffer of delay $d$ on the path. Find the minimum $d$ , and confirm setup still passes if the buffer's max delay is also $d$ and $T = 5$ ns.

Forecast: How much delay closes a $- 0.2$ ns hold gap? Will adding it break setup at $T = 5$ ns?

Step 1 — solve the hold inequality for $d$ . Why this step? Adding a buffer raises $t_{l o g i c}^{min}$ from $0$ to $d$ ; we need $t_{c q}^{min} + d \geq t_{h}$ . $0.1 + d \geq 0.3 \Rightarrow d \geq 0.2 ns$ Choose $d = 0.2$ ns. Step 2 — re-check setup with the buffer's max delay $= 0.2$ ns. Why this step? A buffer also lengthens the slow path, so it eats setup slack. We must confirm it still fits. $S_{se t u p} = T - (t_{c q}^{ma x} + d + t_{s u}) = 5 - (0.5 + 0.2 + 0.4) = 5 - 1.1 = 3.9 ns > 0 ✓$

Verify: New hold slack $= (0.1 + 0.2) - 0.3 = 0.0$ ns — exactly closed. Setup slack $3.9$ ns still huge. ✓ The lesson: buffers fix hold cheaply when $T$ is generous. See STA for automated buffer insertion.

Cell H — limiting cases

Worked example Ex 8 (Cell H)

Two limits with base numbers $t_{c q}^{min} = 0.2$ , $t_{l o g i c}^{min} = 0.3$ , $t_{h} = 0.4$ (base), $t_{c q}^{ma x} = 0.6$ , $t_{l o g i c}^{ma x} = 3.4$ , $t_{s u} = 0.5$ ns. (a) Let $t_{h} \to 0$ . (b) Let $T \to \infty$ (very slow clock).

Forecast: In (a) does hold ever fail? In (b) does setup ever fail — and does hold change?

Step 1 — limit (a): $t_{h} = 0$ . Why this step? Hold slack $= (t_{c q}^{min} + t_{l o g i c}^{min}) - t_{h}$ . Set $t_{h} = 0$ . $S_{h o l d} = (0.2 + 0.3) - 0 = 0.5 ns > 0 \Rightarrow hold can NEVER fail when t_{h} = 0$ Step 2 — limit (b): $T \to \infty$ , setup side. Why this step? Setup slack $= T - (t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u})$ . As $T$ grows, slack grows without bound. $S_{se t u p} = T - 4.5 \to + \infty \Rightarrow setup always passes for large T$ Step 3 — limit (b): $T \to \infty$ , hold side (write it out). Why this step? We must show, not assert, that $T$ does not appear in hold. Compute hold slack at the base $t_{h} = 0.4$ — it contains no $T$ term: $S_{h o l d} = (0.2 + 0.3) - 0.4 = 0.5 - 0.4 = 0.1 ns (independent of T)$ So at $T = 8$ ns it is $0.1$ ns, and at $T = 1000$ ns it is still $0.1$ ns.

Verify: At $t_{h} = 0$ : $0.5 - 0 = 0.5 > 0$ ✓. At $T = 1000$ ns: $S_{se t u p} = 1000 - 4.5 = 995.5 > 0$ ✓ while $S_{h o l d} = 0.1$ ns unchanged. This is exactly why "slow the clock" is a setup-only fix. ✓

Cell I — real-world word problem

Worked example Ex 9 (Cell I)

"A datasheet lists a flip-flop with $t_{c q}^{ma x} = 0.8$ ns, $t_{c q}^{min} = 0.2$ ns, $t_{s u} = 0.3$ ns, $t_{h} = 0.35$ ns. Your logic block has worst-case delay $t_{l o g i c}^{ma x} = 6.4$ ns and fastest-path delay $t_{l o g i c}^{min} = 0.5$ ns. Marketing needs the chip to run at 125 MHz. Does it meet spec (setup and hold), and what is the most logic delay you may allow on the slow path?"

Forecast: $125$ MHz means $T = 8$ ns. Add up $0.8 + 6.4 + 0.3$ . Fit in $8$ ns? And separately, is the fast path long enough for hold?

Step 1 — translate the frequency to a period. Why this step? Constraints are written in time; convert the spec. $T = \frac{1}{125 MHz} = \frac{1}{125 \times 1 0 ^{6} s} = 8 ns$ Step 2 — apply the setup constraint and get slack. Why this step? Meeting the frequency spec = setup slack $\geq 0$ at $T = 8$ ns. $S_{se t u p} = 8 - (0.8 + 6.4 + 0.3) = 8 - 7.5 = 0.5 ns \geq 0 ✓ setup meets spec$ Step 3 — solve setup for the maximum allowed slow-path delay. Why this step? Rearrange $T \geq t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u}$ for $t_{l o g i c}^{ma x}$ to find the ceiling. $t_{l o g i c}^{ma x} \leq 8 - 0.8 - 0.3 = 6.9 ns$ So the slow path may grow from $6.4$ ns up to $6.9$ ns before setup fails. Step 4 — DO NOT skip hold: check the fast path. Why this step? Frequency says nothing about hold; hold is a same-edge race that must be checked independently even in a word problem. Rule: $t_{c q}^{min} + t_{l o g i c}^{min} \geq t_{h}$ . $0.2 + 0.5 = 0.7 ns \geq 0.35 ns ? \Rightarrow TRUE = hold meets spec$

Verify: Setup slack $8 - 7.5 = 0.5$ ns, and the ceiling check is consistent: $6.9 - 6.4 = 0.5$ ns of headroom. Hold slack $0.7 - 0.35 = 0.35$ ns $> 0$ . Both pass → the part meets the $125$ MHz spec. ✓

Cell J — exam twist: skew breaks a passing circuit

Worked example Ex 10 (Cell J)

A circuit passes both checks at skew $= 0$ : hold slack $= 0.35$ ns ( $t_{c q}^{min} + t_{l o g i c}^{min} = 0.75$ , $t_{h} = 0.4$ ). Question: what range of positive capture skew keeps hold safe, and at what skew does it break?

Forecast: Positive skew eats hold slack $1 : 1$ . How much can $0.35$ ns absorb?

Step 1 — write hold with skew. Why this step? Positive capture skew extends the window: need $t_{c q}^{min} + t_{l o g i c}^{min} \geq t_{h} + t_{s k e w}$ . $0.75 \geq 0.4 + t_{s k e w} \Rightarrow t_{s k e w} \leq 0.35 ns$ Step 2 — find the breaking point. Why this step? Hold fails the instant slack goes negative. $S_{h o l d} (t_{s k e w}) = 0.75 - (0.4 + t_{s k e w}) = 0.35 - t_{s k e w}$ Set $= 0$ : breaks at $t_{s k e w} = 0.35$ ns; any $t_{s k e w} > 0.35$ ns → violation.

Verify: At $t_{s k e w} = 0.35$ : $0.35 - 0.35 = 0$ (exact edge). At $t_{s k e w} = 0.5$ : $0.35 - 0.5 = - 0.15$ ns (fails). ✓ Moral: skew you didn't budget for can kill a circuit that "passed" on paper — the heart of the Clock Skew and Jitter problem.

Connections

Parent: Setup and Hold Time Constraints — the derivations these examples exercise.
Static Timing Analysis (STA) — tools that compute the slacks in Ex 3–10 automatically.
Clock Skew and Jitter — the source of the $t_{s k e w}$ in Ex 4, 5, 10.
Pipelining — why register-to-register (Ex 6) timing matters.
Combinational Logic Delay — where $t_{l o g i c}^{ma x}$ and $t_{l o g i c}^{min}$ come from.
Metastability — the failure a violated window produces.
Flip-Flops and Latches — the parts whose $t_{c q}$ , $t_{s u}$ , $t_{h}$ these are.