Exercises — Setup and hold time constraints

WHAT: The setup constraint contains $T$; the hold constraint does not. WHY: Setup is a race across a whole period — data launched by this edge must land before the next edge at time $T$. Hold is a race within one edge — new data vs. the same flip-flop's own keep-still window — so $T$ cancels out. Consequence:

• Setup failure → make $T$ bigger (slow the clock).
• Hold failure → $T$ is irrelevant; add delay (buffers) on the fast path.

Setup: we fear data arriving too late, so we test the slowest (propagation) path → use $t_{cq}^{max}$, $t_{logic}^{max}$. Hold: we fear data arriving too early and corrupting the current capture, so we test the fastest (contamination) path → use $t_{cq}^{min}$, $t_{logic}^{min}$.

Step 1 — pick the constraint. Frequency is limited by setup (the one with $T$). Step 2 — build the period from the timeline. Trace one edge: after the launching edge, Q at FF1 needs $t_{cq}^{max}$ to appear, then the signal needs $t_{logic}^{max}$ to cross the logic, and then FF2 needs the data to sit still for $t_{su}$ before the capture edge. Those three durations happen back-to-back inside one period and must all fit before the next edge — so their sum is the smallest period that still fits: $T_{min}=t_{cq}^{max}+t_{logic}^{max}+t_{su}=0.5+2.7+0.3=3.5\text{ns}$ That is why we add exactly these three terms: they are the only things consuming time between one edge and the reserved setup window of the next. Step 3 — invert (because $f=1/T$; a shorter period means more edges per second): $f_{max}=\frac{1}{3.5\text{ns}}=285.7\text{MHz}$

Step 1 — earliest data change at FF2's input after the edge. We use the fastest (contamination) numbers because the earliest possible disturbance is the danger: $t_{cq}^{min}+t_{logic}^{min}=0.15+0.20=0.35\text{ns}$ Step 2 — compare to $t_h$: FF2 needs its input frozen for $t_h$ after the edge, so we need $0.35\ge 0.45$. It is not → HOLD VIOLATION (margin $=0.35-0.45=-0.10$ ns). Step 3 — fix by lengthening the fast path so the earliest change lands after the hold window, $0.35+d\ge 0.45$: $d\ge 0.10\text{ns}$

Step 1 — start from the setup inequality: $T+t_{skew}\ge t_{cq}^{max}+t_{logic}^{max}+t_{su}$. Step 2 — rearrange, and read what it means. We want the smallest $T$ that still satisfies this, so we move $t_{skew}$ to the right-hand side (subtract it from both sides) and treat the inequality at its tightest (equality): $T_{min}=(t_{cq}^{max}+t_{logic}^{max}+t_{su})-t_{skew}$ Physical meaning of the minus: a later capture edge (positive skew) is like being handed extra free time on top of the period. So the period itself no longer has to cover the full delay sum — skew donates $t_{skew}$ of it. Numerically: $T_{min}=(0.5+3.6+0.4)-0.4=4.5-0.4=4.1\text{ns}$ $f_{max}=\frac{1}{4.1\text{ns}}=243.9\text{MHz}$ Compare: zero-skew $T_{min}=4.5$ ns → $222.2$ MHz. Positive capture skew relaxes setup (the capture edge is later, giving data more time), so $f_{max}$ rises. Look at the figure: pushing the capture edge right widens the usable arrival region.

Zero skew: earliest change (contamination path) is $0.20+0.35=0.55$; need $0.55\ge 0.30$. ✓ Safe, margin $+0.25$ ns. Skew $=0.4$: hold becomes $t_{cq}^{min}+t_{logic}^{min}\ge t_h+t_{skew}=0.30+0.40=0.70$. A later capture edge stretches the keep-still window further into the future, so the fast data must arrive even later. Check: $0.55\ge 0.70$? No → now VIOLATED, margin $0.55-0.70=-0.15$ ns. Fix: add $d$ with $0.55+d\ge 0.70\Rightarrow d\ge 0.15$ ns. Insight: the same skew that gave us free speed in 3.1 broke hold here. Skew is a trade, never free.

Step 1 — period from frequency: $T=1/(500\text{MHz})=2.0$ ns. Step 2 — rearrange setup for the logic budget. The setup rule says the three durations ($t_{cq}^{max}$, $t_{logic}^{max}$, $t_{su}$) must fit inside $T$. Solving for the one unknown means subtracting the two fixed terms from the period — whatever is left over is all the time the logic is allowed to spend: $t_{logic}^{max}\le T-t_{cq}^{max}-t_{su}=2.0-0.4-0.25=1.35\text{ns}$ (a) Budget $=1.35$ ns. (b) Actual $2.1$ ns $>1.35$ ns → fails setup. Slack $=1.35-2.1=-0.75$ ns (negative = violation). You must cut $0.75$ ns of logic delay (or slow the clock, or add skew).

Hold side (lower bound on the fast/contamination path). Rearranging the hold rule for the unknown fast delay means subtracting the fixed $t_{cq}^{min}$ from $t_h$ — the fast path must be at least long enough to cover the leftover: $t_{logic}^{min}\ge t_h-t_{cq}^{min}=0.60-0.15=0.45\text{ns}$ Setup side (upper bound on the slow/propagation path): $1.35$ ns (from 4.1). Window: logic must satisfy $0.45\text{ns}\le t_{logic}\le 1.35\text{ns}$. Since $0.45<1.35$, the window is non-empty → a valid design exists. (If the lower bound had exceeded the upper bound, no single logic block could satisfy both, and you'd need clock-tree or buffer surgery.)

(a) Hold with skew: requirement is $t_{cq}^{min}+t_{logic}^{min}\ge t_h+t_{skew}$: $0.30\ge 0.50+(-0.25)=0.25✓$ Hold now passes (margin $0.30-0.25=+0.05$ ns). Negative capture skew shrinks the effective hold window — the mirror image of positive skew in Ex 3.2. (b) Setup with the same skew: $T+t_{skew}\ge t_{cq}^{max}+t_{logic}^{max}+t_{su}$: $4.0+(-0.25)=3.75\ge 0.5+3.0+0.3=3.8?$ $3.75\ge 3.8$ is false → setup now fails (margin $3.75-3.8=-0.05$ ns). Verdict: negative skew traded a hold failure for a setup failure. The path does not pass both. Buffers on the fast path (which touch only hold) would have been the clean fix.

Setup slack $=$ (available time) $-$ (required time), and jitter steals from the available period, so we subtract it too: $\text{setup slack}=(T-t_{jitter}-t_{su})-(t_{cq}^{max}+t_{logic}^{max})$ $=(5.0-0.15-0.4)-(0.6+3.8)=4.45-4.4=+0.05\text{ns}\Rightarrow \text{PASS}$ (Without the jitter charge it would have been $+0.20$ ns — jitter ate $0.15$ ns of margin.) Hold slack $=$ (earliest data change, contamination path) $-$ (required hold): $=(t_{cq}^{min}+t_{logic}^{min})-t_h=(0.10+0.25)-0.35=0.00\text{ns}\Rightarrow \text{PASS (exactly on the edge)}$ Sign-off: setup margin shrank to $+0.05$ ns once jitter was charged; hold margin is $0.00$ ns. Both pass, but both are razor-thin — any extra variation tips either into violation. Flag for a small buffer (hold) and margin review (setup). Look at the slack picture: setup slack is the gap before the red band; hold slack is the gap after the edge.

Every problem on this page is one of two questions. "Did the note arrive before the next clap?" → setup, involves the period $T$, fix by clapping slower / trimming logic / positive capture skew. "Did we hold the note long enough after this clap?" → hold, no $T$, fix by holding longer (buffers) — and beware skew, which quietly changes the shape of the keep-still window in opposite directions for the two checks.