Setup and hold time constraints: Visual walkthrough

This is the visual companion to the parent topic. If any word here is new, it is defined on its own step, on its own picture.

Step 1 — What a clock edge is, on a timeline

WHAT. Draw a horizontal line for time flowing left → right. A clock is a signal that goes low–high–low–high forever. The moment it jumps up is the active edge — the instant the flip-flop "takes its photo" of the data.

WHY start here. Every later rule is measured relative to an edge. If we don't fix where the edge sits on the timeline, no "before" or "after" has meaning.

PICTURE. Below, the burnt-orange vertical line is one active edge. We place it at time $t = 0$ as our reference. The next edge is one clock period $T$ later.

Figure — Setup and hold time constraints

$t = 0$ → launching edge (data leaves here)
$t = T$ → capturing edge (data must be caught here)

Step 2 — The "keep-still" window around an edge

WHAT. Zoom into one edge. The flip-flop demands the data input D be frozen for a tiny stretch before the edge and a tiny stretch after it.

WHY. A flip-flop stores a bit using gates that feed back into themselves (a loop). The loop needs a still target to lock onto. If D is sliding when the edge hits, the loop can get stuck halfway = metastability (see Metastability).

PICTURE. The plum band is the forbidden zone. Its left half has width $t_{s u}$ , its right half has width $t_{h}$ .

The window is the interval $[- t_{s u}, + t_{h}]$ measured from the edge. Notice two independent deadlines — that is exactly why we will get two constraints.

Step 3 — The two-flop pipeline: where data travels

WHAT. Put two flip-flops side by side. FF1 launches data; it travels through a block of plain gates (combinational logic, see Combinational Logic Delay); it arrives at FF2's D. Both flops share the same clock (see Pipelining).

WHY. A single flop can't violate anything by itself — it needs a source of data and a deadline. FF1 is the source, FF2's next edge is the deadline. This is the smallest circuit where setup/hold actually bite.

PICTURE. Teal path = the data's journey. It starts at FF1's Q, crosses the logic cloud, ends at FF2's D.

Step 4 — SETUP: the race across a whole period

WHAT. Follow the slowest possible data. It leaves FF1 late (after $t_{c q}^{ma x}$ ), crawls through the logic (after $t_{l o g i c}^{ma x}$ ), and must still land before FF2's setup window opens at the next edge $T$ .

WHY the slowest path? Setup fails when data is too late. The worst enemy of "in time" is the slowest route — so we test with the maximum delays.

PICTURE. The teal arrow is the late data crawling toward $t = T$ . The plum band on the right is FF2's setup window it must not enter.

Arrival time of the new data at FF2's D:

$t_{a r r i v e} = FF1 wakes late t_{c q}^{ma x} + slow crawl through gates t_{l o g i c}^{ma x}$

The deadline: the arrival must beat the opening of FF2's setup window, which is $t_{s u}$ before $T$ :

$t_{a r r i v e} \leq next edge T - reserved keep-still t_{s u}$

Substitute and rearrange — WHY subtract $t_{s u}$ ? we must reserve the last $t_{s u}$ seconds of the period as forbidden:

Step 5 — HOLD: the race inside a single edge

WHAT. Now the danger is the opposite: the fastest data. On the very same launching edge, FF1 might spit out new data so quickly that it races through the logic and overwrites the value FF2 is still trying to latch on this edge.

WHY the fastest path? Hold fails when data arrives too early. The worst enemy of "not too soon" is the fastest route — so we test with the minimum delays.

PICTURE. The teal arrow is short and stubby: fast data leaving right after $t = 0$ , threatening FF2's hold band (right half of the window).

Earliest the new data can reach FF2's D:

$t_{e a r l y} = FF1 wakes fast t_{c q}^{min} + quick dash through gates t_{l o g i c}^{min}$

FF2 needs D frozen until $t_{h}$ after the edge. So the earliest disturbance must come no sooner than $t_{h}$ :

Step 6 — Clock skew: the same lever, opposite ends

WHAT. Suppose the capturing clock reaches FF2 later than the launching clock by an amount $t_{s k e w}$ (positive = capture edge delayed). This shifts FF2's whole window to the right (see Clock Skew and Jitter).

WHY it matters twice. Moving FF2's edge later gives slow data more room (setup easier) but drags the hold band further into the fast data (hold harder). One knob, two opposite effects.

PICTURE. Grey = original FF2 window; plum = shifted-right window. The right shift opens a gap for setup but closes in on the fast teal arrow for hold.

$setup gets extra time T + t_{s k e w} \geq t_{c q}^{ma x} + t_{l o g i c}^{ma x} + t_{s u}$

$t_{c q}^{min} + t_{l o g i c}^{min} \geq hold needs even more calm t_{h} + t_{s k e w}$

Step 7 — Degenerate & edge cases (never get surprised)

WHAT / WHY. Rules must survive the weird corners. Here is every boundary.

Zero logic between flops ( $t_{l o g i c}^{min} = 0$ , two flops back-to-back): hold becomes $t_{c q}^{min} \geq t_{h}$ . If the flop's own $t_{c q}^{min} < t_{h}$ , shift registers would fail — real flops are designed so $t_{c q}^{min} \geq t_{h}$ to make this safe.
Exact equality ( $t_{e a r l y} = t_{h}$ ): the margin is zero. Technically passes, but any jitter tips it into failure. Treat zero margin as risky.
Negative computed margin: means a violation, not a negative time — the data physically arrives inside the forbidden band.
$T \to \infty$ (clock stopped): setup is trivially satisfied ( $T$ huge), hold is unchanged — proving again hold ignores $T$ .
Negative skew (capture edge earlier): flips Step 6 — setup gets harder, hold gets easier.

The bars show margin = (available) − (required). Green above zero = pass; red below = violation.

The one-picture summary

Everything at once: one launching edge at $0$ , one capturing edge at $T$ , FF2's window drawn twice (setup half on the left of $T$ , hold half just after $0$ ), and the two arrows — the slow one fighting setup, the fast one fighting hold.

Recall Feynman: the whole walkthrough in plain words

A clock ticks, and each tick is a camera shutter. Around every shutter there's a "please freeze" window: freeze a little before (setup) and a little after (hold). We line up two cameras. The first fires, its picture crawls through some gates, and must reach the second camera before its next shutter's freeze window opens — if it's too slow, we just click slower (bigger $T$ ) and it makes it. But there's a sneakier danger: right after the first shutter, the first camera might fire out new data so fast that it smears the picture the second camera is still saving from this click. Clicking slower doesn't help — both events belong to the same click — so we slow the fast path down with buffers instead. Finally, if the second camera's clock is delayed a bit (skew), the slow race gets easier but the fast race gets worse: one knob, two opposite pulls.

Connections

Setup and hold time constraints — the parent topic this page illustrates.
Flip-Flops and Latches — the device whose window we drew.
Metastability — what happens if the window is violated.
Clock Skew and Jitter — Step 6's shifting edge.
Static Timing Analysis (STA) — automates these two checks over a whole chip.
Combinational Logic Delay — the $t_{l o g i c}$ cloud.
Pipelining — why two flops with logic between them is the normal case.