Setup and hold time constraints: Foundations — Hardware deep dive

Before you can read a single line of the parent note, you need to know what a clock edge is, what a wire being "stable" means, what each little timing symbol ( $t_{s u}$ , $t_{h}$ , $t_{c q}$ , $T$ , $t_{s k e w}$ ) measures, and how "delay" turns into a picture on a timeline. This page builds all of them from zero, in an order where each one leans only on the ones before it.

0. The one object everything sits on: a signal on a timeline

Every symbol in this topic is a length of time measured along a horizontal line. So we must first agree on how to draw a signal over time.

A signal is a wire whose voltage is either low (we call it 0) or high (we call it 1). Drawn against time, it looks like a staircase: flat while the value holds, a steep ramp where it switches.

Why the topic needs this: setup and hold are rules about when the staircase is allowed to have a ramp. If you can't picture "flat vs. ramp on a timeline," none of the constraints mean anything.

1. The clock and its edge

The little arrow on the rising ramp is the shutter click. Everything in this topic is measured relative to that arrow: "before the edge" = to its left, "after the edge" = to its right.

Why the topic needs it: setup time lives left of the arrow, hold time lives right of it. No edge → no reference point → no constraint.

2. The clock period $T$

Look at the two arrows in the figure above: the gap between them is $T$ .

Why we need $T$ : it is the total budget of time the data has to travel from one flip-flop to the next. The whole setup constraint is the sentence "your journey must fit inside $T$ ."

3. "Delay" — the width of a journey on the timeline

Signals don't teleport. When a gate or wire processes a value, the new value appears later than the cause. That lateness is a delay — again, just a horizontal length on the timeline.

Why we need both min and max: setup asks "what if it's too slow?" (uses $t^{ma x}$ ). Hold asks "what if it's too fast?" (uses $t^{min}$ ). Two opposite fears → two different delay numbers. This is exactly the parent note's "Setup uses MAX, Hold uses MIN."

4. The three flip-flop timing numbers: $t_{s u}$ , $t_{h}$ , $t_{c q}$

Now that "a length of time on the timeline" is second nature, the flip-flop's own three numbers are easy — they are just three specific lengths measured from the active-edge arrow.

5. Clock skew $t_{s k e w}$ — when two clocks don't tick together

We assumed both flip-flops hear the clock at the same instant. In a real chip the clock wire is longer to some flip-flops, so their edge arrives later.

Picture: two shutter-click arrows that should line up vertically, but the second one is shifted right by $t_{s k e w}$ .

Why we need it: shifting the capture arrow right gives data more room before it (setup gets easier) but stretches the keep-still window into the fast data (hold gets harder) — the parent note's central trade-off.

6. The pipeline: two flip-flops with logic between

Trace it: timeline and edge are the ground floor; period, delay, and the three flip-flop numbers sit on them; those combine into the setup and hold constraints, and skew tilts both — which is exactly the parent topic.

Equipment checklist

Cover the right side and answer out loud. If any stumps you, re-read that section before opening the parent note.

What does it mean for a signal to be "stable"?

Its value is flat — not transitioning — on the timeline (no ramp there).

What is the active edge of a clock?

The chosen clock transition (we use rising, 0→1) at which the flip-flop samples its data — the "shutter click."

What is the clock period

T

, in one phrase?

The time between one active edge and the next.

How are frequency

f

and period

T

related, and why?

f = 1/ T

; if one edge takes

T

seconds, you fit

1/ T

of them per second.

What is a "delay" on a timeline?

The horizontal gap between a cause and when its effect appears.

Why does every path have both a

t^{ma x}

and a

t^{min}

Because real delays vary; setup fears the slowest (

t^{ma x}

), hold fears the fastest (

t^{min}

Where does setup time

t_{s u}

sit relative to the edge?

In the window before the edge — D must be flat there.

Where does hold time

t_{h}

sit relative to the edge?

In the window after the edge — D must stay flat there.

What does

t_{c q}

measure, and is it about input or output?

The delay from the edge until output Q appears — it's about the output.

What is clock skew

t_{s k e w}

(with our sign convention)?

The difference in edge-arrival time between two flip-flops; positive means the capturing flip-flop's edge is delayed.

In the pipeline, which flip-flop "launches" and which "captures"?

FF1 launches data through the logic; FF2 captures it — FF2's input D is what we protect.

Connections

↑ Parent: Setup and hold time constraints — where these symbols get assembled into the two inequalities.
Flip-Flops and Latches — the device that defines $t_{s u}$ , $t_{h}$ , and $t_{c q}$ .
Combinational Logic Delay — where $t_{l o g i c}^{ma x}$ and $t_{l o g i c}^{min}$ come from.
Clock Skew and Jitter — deeper dive on $t_{s k e w}$ .
Metastability — what breaks when the keep-still window is violated.
Static Timing Analysis (STA) — the tool that checks these constraints automatically.
Pipelining — why we chain launch–capture pairs in the first place.