Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7)
WHY does this family exist?
WHY a family instead of one chip? Because embedded needs span a huge range:
- A $0.20 sensor that just toggles a pin → wants the cheapest, lowest-power core (M0).
- A motor controller doing PID math at 20 kHz → wants fast multiply + maybe floating point (M4).
- A camera pipeline doing FFTs → wants caches and high clock (M7).
One core can't be optimal for all, so ARM segments them.
The four cores at a glance
| Core | Pipeline | Architecture | DSP (SIMD) | FPU | Cache/MPU | Typical clock |
|---|---|---|---|---|---|---|
| M0/M0+ | 2-stage | ARMv6-M | ❌ | ❌ | optional MPU | ~48 MHz |
| M3 | 3-stage | ARMv7-M | ❌ | ❌ | MPU | ~72–120 MHz |
| M4 | 3-stage | ARMv7E-M | ✅ SIMD/DSP | optional single-precision | MPU | ~100–180 MHz |
| M7 | 6-stage, dual-issue | ARMv7E-M | ✅ | optional single +double | I/D caches, MPU | ~300–600 MHz |
HOW the architecture is built (first principles)
1. Harvard-ish bus & the pipeline
A CPU does: Fetch instruction → Decode it → Execute it. If done one-at-a-time, each instruction takes 3 clock cycles. A pipeline overlaps them like an assembly line.
Why does M7 add a 6th stage + dual-issue? Two reasons:
- Shorter logic per stage → you can clock the chip higher (more MHz).
- Dual-issue (superscalar): fetch/decode two instructions per cycle → can exceed 1.
2. The interrupt machine: NVIC + exception model
The defining feature of Cortex-M for real-time is the NVIC (Nested Vectored Interrupt Controller).
3. Two stacks, two modes
Cortex-M has MSP (Main Stack Pointer) and PSP (Process Stack Pointer), plus Handler mode (interrupts) vs Thread mode (normal code). WHY two stacks? So an RTOS can give each task its own PSP stack while interrupts use the shared MSP — a crash in one task's stack can't corrupt the kernel's.
4. Memory-mapped everything
There are no special I/O instructions. A GPIO register lives at a fixed address like 0x40020000. You read/write it with a normal load/store. WHY? Simplicity + one uniform addressing model = simpler core = lower power.
Worked examples
Common mistakes (Steel-man + fix)
Recall Feynman: explain it to a 12-year-old
Imagine four robots that all read the same simple instruction cards.
- M0 is a small cheap robot — it reads one card at a time, slow but sips almost no power.
- M3 is a bit smarter and reads cards on a little conveyor belt so it never waits.
- M4 has a calculator built into its hand — it can multiply huge numbers instantly (great for music/sound robots).
- M7 is the big one: it reads two cards at once, runs super fast, and keeps a tiny notebook of stuff it just used (a cache) so it doesn't run back to the shelf. The clever robot trick they ALL share: when someone shouts "emergency!" (an interrupt), they instantly drop a bookmark (save registers) and jump to fix it in the exact same time, every time — that "every time the same" is why they run rockets and pacemakers.
Flashcards
What instruction set do all Cortex-M cores execute?
How many registers does the NVIC auto-stack on an interrupt, and which?
Why is the Cortex-M interrupt latency called "deterministic"?
What does "vectored" mean in NVIC?
M0 vs M7 pipeline depth?
The big trap of the M4 FPU?
double math falls back to slow software emulation.Which Cortex-M can do double-precision FP in hardware?
What feature distinguishes M4 from M3 numerically?
Formula for cycles to run I instructions through an N-stage pipeline (no stalls)?
Why two stack pointers (MSP/PSP)?
Why might an M0+ be better for real-time than M7?
How do you reach a peripheral register on Cortex-M?
What register enables the FPU, and what happens if you forget?
What memory gives M7 guaranteed timing despite caches?
Connections
- Interrupts and the NVIC
- RTOS task scheduling and context switching
- Pipelining and superscalar execution
- Fixed-point vs floating-point DSP
- Memory-mapped I/O and GPIO
- Memory Protection Unit (MPU)
- IEEE-754 floating point
- Cache vs TCM in real-time systems
Concept Map
Hinglish (regional understanding)
Intuition Hinglish mein samjho
Dekho, Cortex-M ek 32-bit RISC processor core hai jo microcontroller ke andar baitha rehta hai — yeh desktop CPU nahi hai, yeh chhote, deterministic, low-power, real-time kaam ke liye banaya gaya hai. M0 se M7 tak ek seedhi (ladder) samjho: jaise upar chadhte ho, core ko zyada instructions samajh aate hain, fetch karne ke faster tareeke milte hain, aur special math hardware (DSP, FPU) add hota hai. Lekin yeh upgrade free nahi hai — power aur silicon area mehnga padta hai. Isliye asli skill yeh hai: jo sabse chhota core tumhara deadline meet kare, wahi choose karo.
Pipeline ka funda simple hai: Fetch → Decode → Execute ek assembly line ki tarah overlap hote hain, isliye pipe bharne ke baad har cycle mein ek instruction nikalta hai. M7 mein 6-stage + dual-issue hai matlab ek hi cycle mein do instructions — isliye woh sabse fast hai, plus uske paas cache bhi hai. Par yaad rakho: deeper pipeline ka matlab "always faster" nahi — branch miss ka penalty bhi badhta hai, aur cache se timing data-dependent ho jaati hai, jo hard real-time ke liye risky hai.
Cortex-M ka sabse important hero hai NVIC — jab interrupt aata hai, hardware khud 8 registers stack pe push kar deta hai aur vector table se seedha handler pe jump karta hai, fixed cycles (~12) mein. Isi "har baar same time" ki wajah se inhe pacemaker, motor control, drones mein use karte hain. Aur ek bada trap: M4 ka FPU sirf single-precision hai — agar tum double use karoge to wapas slow software emulation chalu ho jaayega. float aur sinf use karo, aur FPU ko CPACR register mein enable karna mat bhoolna warna HardFault aa jaayega!