Before you can read the parent note ARM Cortex-M Series, you need every word and symbol it throws at you. We build each one from nothing, in an order where each idea leans on the one before it.
Picture it: imagine 8 light switches in a row. Each switch is a bit; the whole row is a byte. The pattern of ON/OFF switches is the number stored.
Why "32-bit"? When the parent says Cortex-M is a 32-bit core, it means the CPU's basic "hands" — the registers it does math with, and the addresses it points at — are 32 wires wide. That gives:
Why does embedded code love hex? Because one hex digit is exactly 4 bits. So two hex digits = 1 byte, and 8 hex digits = 32 bits. An address like 0x40020000 is 32 bits written compactly.
Question: how many bits does the hex number 0x40020000 represent?
Why the topic needs this: the parent says peripherals are memory-mapped — a GPIO control register "lives at" 0x40020000. That means one specific house on this street is wired not to a memory cell but to a physical pin controller. Writing a number into that house toggles hardware. See Memory-mapped I/O and GPIO.
A single house holds one byte. But a 32-bit value needs four houses in a row. Two low-level rules decide how those four bytes sit — and getting them wrong corrupts every load and store.
Why it matters here: when you read a peripheral register or a value in memory, the CPU reassembles the bytes using this order. If you assumed the wrong order (say, sharing data with a big-endian device), the number comes out scrambled. So "little-endian" is a fact you must carry into every memory-mapped I/O discussion.
Recall On a little-endian Cortex-M, where does the least-significant byte of a word go?
Picture it: if memory is a warehouse across town, registers are the few items in your pockets — instant to reach, but you only have a handful. The CPU can only do math on values sitting in registers, so work is a constant shuttle: load from memory → compute in registers → store back.
The named registers the parent lists (and you must recognise):
Name
Plain meaning
R0–R12
general-purpose pockets for your data
PC (Program Counter)
address of the next instruction to run
LR (Link Register)
the "return address" — where to go back to after a function
xPSR
status flags (was the last result zero? negative? etc.)
MSP / PSP
two different Stack Pointers (see §7)
Recall Why can't the CPU compute directly on memory?
Because arithmetic hardware is wired only to the registers. Memory is reached only through explicit load/store steps — this simplicity keeps the core small and low-power.
Fetch — read the next instruction from memory (address given by PC).
Decode — figure out what it means.
Execute — actually do it.
Why the topic needs this: if each instruction waited for all three beats, one instruction = 3 clock ticks. The pipeline (parent §1) overlaps them like an assembly line — this rhythm is exactly what a pipeline speeds up. See Pipelining and superscalar execution.
Why smaller matters here: embedded chips have tiny memories. A shorter encoding means more program fits in the same flash, and fetching costs fewer bytes. RISC (Reduced Instruction Set Computer) means the vocabulary is deliberately small and regular — simpler to build, easier to pipeline.
Why the topic needs it: when an interrupt fires, the CPU must push your current registers onto the stack so it can restore them later — the "automatic stacking" the NVIC does. And functions push their return address (LR) and locals here.
Why TWO stacks (MSP + PSP)? So a normal task's scratch pile (PSP) is kept separate from the interrupt/kernel pile (MSP). If one task overflows its stack, it cannot smash the kernel's. This split powers RTOS isolation — see RTOS task scheduling and context switching.
Picture it: you're reading a book (main program). The doorbell rings (interrupt). You bookmark the page (push registers), answer the door (run handler), then return to your exact line (pop registers). The bookmark is the stack push from §7.
Why it defines real-time: the whole selling point of Cortex-M is that this "answer the door" time is bounded and knowable. That controller is the NVIC defined above — see Interrupts and the NVIC.
Why both exist: cache is fast on average but a "miss" is slow, so timing becomes unpredictable — bad for hard deadlines. TCM trades size for guaranteed timing. This tension is the M7 story: Cache vs TCM in real-time systems.
Each arrow means "you need the left box before the right box makes sense." Notice everything funnels into the single Cortex-M topic node — that is the parent page.
