Parent note ARM Cortex-M Series padhne se pehle, us mein aane wale har word aur symbol ko samajhna zaroori hai. Hum har ek cheez ko zero se build karenge, ek aisi order mein jahan har idea apne pehle wale idea par lean karta hai.
Imagine karo: 8 light switches ki ek row hai. Har switch ek bit hai; poori row ek byte hai. ON/OFF switches ka pattern hi stored number hai.
"32-bit" kyun? Jab parent kehta hai Cortex-M ek 32-bit core hai, toh matlab hai ki CPU ke basic "haath" — registers jisme woh math karta hai, aur addresses jinhein woh point karta hai — 32 wires wide hain. Isse milta hai:
Topic ko yeh kyun chahiye: parent kehta hai ki peripherals memory-mapped hote hain — ek GPIO control register 0x40020000 par "rehta hai". Matlab is street par ek specific ghar memory cell se nahi balki ek physical pin controller se wired hai. Us ghar mein number likhne se hardware toggle ho jaata hai. Dekho Memory-mapped I/O and GPIO.
Ek single ghar ek byte hold karta hai. Lekin ek 32-bit value ko chaar ghar row mein chahiye. Do low-level rules decide karte hain ki woh chaar bytes kaise baithenge — aur galat karna har load aur store corrupt kar deta hai.
Yeh kyun matter karta hai: jab tum koi peripheral register ya memory mein koi value padhte ho, toh CPU bytes ko is order ke hisaab se reassemble karta hai. Agar tumne galat order assume kiya (maan lo kisi big-endian device ke saath data share kar rahe ho), toh number scrambled nikal aata hai. Isliye "little-endian" ek aisi fact hai jo tumhare paas har memory-mapped I/O discussion mein honi chahiye.
Recall Little-endian Cortex-M par, ek word ka least-significant byte kahan jaata hai?
Imagine karo: agar memory sheher ke paar ek warehouse hai, toh registers tumhari jeb mein rakhi kuch cheezein hain — turant reach ho sakti hain, lekin sirf mutthi bhar hain. CPU sirf registers mein baithe values par math kar sakta hai, isliye kaam ek constant shuttle hai: memory se load karo → registers mein compute karo → wapas store karo.
Named registers jo parent list karta hai (aur jinhe tumhein pehchanana hai):
Naam
Seedha matlab
R0–R12
data ke liye general-purpose jebein
PC (Program Counter)
chalane wali agli instruction ka address
LR (Link Register)
"return address" — function ke baad wapas kahan jaana hai
xPSR
status flags (kya last result zero tha? negative? etc.)
MSP / PSP
do alag Stack Pointers (dekho §7)
Recall CPU directly memory par compute kyun nahi kar sakta?
Kyunki arithmetic hardware sirf registers se wired hai. Memory sirf explicit load/store steps ke through reach hoti hai — yeh simplicity core ko small aur low-power rakhti hai.
Fetch — memory se agli instruction padhna (PC ka address use karke).
Decode — yeh pata lagana ki iska matlab kya hai.
Execute — actually woh karna.
Topic ko yeh kyun chahiye: agar har instruction teeno beats ka wait karti, toh ek instruction = 3 clock ticks. Pipeline (parent §1) inhe ek assembly line ki tarah overlap karta hai — yeh rhythm exactly woh hai jise ek pipeline speed up karti hai. Dekho Pipelining and superscalar execution.
Pehle, ek hardware term jis par hum aage lean karenge:
Topic ko yeh kyun chahiye: jab interrupt fire hota hai, toh CPU ko tumhare current registers stack par push karne chahiye taaki baad mein restore kar sake — yeh "automatic stacking" woh hai jo NVIC karta hai. Aur functions apna return address (LR) aur locals yahan push karte hain.
DO stacks (MSP + PSP) kyun? Taaki ek normal task ka scratch pile (PSP) interrupt/kernel pile (MSP) se alag rahe. Agar ek task apna stack overflow kar de, toh woh kernel wale ko nahi tod sakta. Yeh split RTOS isolation power karta hai — dekho RTOS task scheduling and context switching.
Imagine karo: tum ek kitaab padh rahe ho (main program). Doorbell baji (interrupt). Tumne page bookmark kiya (registers push kiye), darwaza khola (handler run kiya), phir wapas apni exact line par aa gaye (registers pop kiye). Bookmark hi §7 wala stack push hai.
Yeh real-time define kyun karta hai: Cortex-M ka poora selling point yeh hai ki yeh "darwaza kholne" wala time bounded aur knowable hai. Woh controller NVIC hai jo upar define hua — dekho Interrupts and the NVIC.
Dono kyun hain: cache average par fast hai lekin ek "miss" slow hota hai, isliye timing unpredictable ho jaati hai — hard deadlines ke liye bura. TCM size ke badle guaranteed timing deta hai. Yahi tension M7 story hai: Cache vs TCM in real-time systems.
Har arrow ka matlab hai "right box samajhne ke liye left box zaroori hai." Notice karo ki sab kuch ek single Cortex-M topic node mein funnel hota hai — woh hi parent page hai.
Right side cover karo aur parent note padhne se pehle har ek ka jawab do.
Ek "byte" mein kitne bits hote hain, aur kitne patterns ho sakte hain?
8 bits, jisse 28=256 patterns milte hain.
0x prefix ka kya matlab hai aur ek hex digit kitne bits encode karta hai?
0x ek hexadecimal number mark karta hai; har hex digit exactly 4 bits encode karta hai.
Ek 32-bit CPU har peripheral ko apna address kyun de sakta hai?
Kyunki 232≈4 billion addresses exist karte hain — name karne ke liye peripherals se kahin zyada.
Peripheral kya hota hai?
CPU ke aas-paas koi bhi controllable hardware block (timer, serial port, ADC, GPIO), jo CPU ko read/write slots ke set ki tarah dikhta hai.
Cortex-M cores by default kaunsa byte order use karte hain?
Little-endian — least-significant byte lowest address par hota hai.
Ek 32-bit word ke liye alignment rule kya hai, aur M0+ par todne par kya hota hai?
Word ek aisi address par shuru honi chahiye jo 4 se divisible ho; M0/M0+ par unaligned access HardFault raise karta hai.
Register aur memory mein kya fark hai?
Registers CPU ke andar kuch ultra-fast slots hain jahan math hota hai; memory ek badi, slower numbered street hai jise load/store se reach kiya jaata hai.
