Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7): Exercises

Intuition How to use this page

Cover the Solution callout, try the problem cold, then reveal. The levels climb the same ladder as the cores: first you just recognise a spec, then you apply the pipeline/latency formulas, then analyse trade-offs, then synthesise a design, then master a nasty edge case. Every numeric answer on this page is machine-checked — see the verification block that ships with this note (each exercise's number is re-derived in sympy). If your answer disagrees with a checked one, trust the check and hunt your slip.

Prerequisites you may want open: the parent topic, Pipelining and superscalar execution, Interrupts and the NVIC, RTOS task scheduling and context switching, Fixed-point vs floating-point DSP, IEEE-754 floating point, Cache vs TCM in real-time systems, Memory-mapped I/O and GPIO, Memory Protection Unit (MPU).

Before we start, let us re-earn the three formulas we will lean on, so no symbol appears unexplained.

Formula The three tools we reuse

1. Pipeline fill. An $N$ -stage pipeline is an assembly line with $N$ work-stations. The first instruction must pass through all $N$ stations before it exits — that costs $N$ cycles. After that, one new instruction exits every cycle. So $I$ instructions take $Cycles = (N - 1) + I .$ Here $N$ = number of pipeline stages (a whole number), $I$ = number of instructions run (a whole number), and a cycle is one tick of the CPU clock.

2. Superscalar IPC. "Issue width" $w$ = how many instructions the core can launch per cycle. "Pairing fraction" $p$ = the fraction (between $0$ and $1$ ) of instructions that actually find a partner to launch alongside. Then instructions-per-cycle is $IPC = 1 + p (w - 1) .$ Why this formula? Think of instructions marching in single file: a lone instruction always gives you IPC $= 1$ (one per cycle). Now, whenever an instruction pairs up, it drags $(w - 1)$ extra friends through in the same cycle for free — but that bonus only happens for the fraction $p$ of instructions that manage to pair. So the average bonus per instruction is $p (w - 1)$ , and you add it to the baseline $1$ : $IPC = 1 + p (w - 1)$ . (Check the ends: $p = 0$ → no pairing → IPC $= 1$ ; $p = 1$ , $w = 2$ → everything pairs → IPC $= 2$ , i.e. twice the work per cycle.) IPC literally means: on average, how many instructions finish each clock tick.

3. Time from cycles. A clock at $f$ MHz ticks $f$ million times per second, so one cycle lasts $1/ f$ microseconds: $t = \frac{Cycles}{f ( MHz )} μ s .$ ( $μ s$ = microsecond = one millionth of a second. We will sometimes zoom in further to $ns$ = nanosecond = one billionth of a second, so $1 μ s = 1000 ns$ — just multiply a µs answer by 1000 to read it in ns.)

The picture below shows exactly why the pipeline-fill formula is $(N - 1) + I$ and not $N \times I$ — read it before Level 2.

Figure — Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7)

Common mistake Reality check: when

$(N - 1) + I$ does not hold exactly Why it feels right: the assembly-line picture is so clean it seems the pipe is always full. The truth: the formula assumes no stalls. In real code the staircase breaks on:

a branch misprediction — the CPU guessed the wrong next instruction, so it must flush the partially-filled pipe and re-fill it, costing roughly another $(N - 1)$ cycles each time. Deeper pipes (M7's 6 stages) hurt more here than an M0+'s 2 stages.
a data hazard / memory stall — an instruction needs a result (or a slow memory word) that isn't ready, so the pipe stalls (inserts bubbles).
an interrupt/exception — control jumps away and the pipe re-fills at the handler. Fix: use $(N - 1) + I$ as the ideal (no-stall) count, then add per-event penalties. Every exercise here says "no stalls" precisely so the ideal formula applies — but worst-case real-time budgets must add the flush terms back.

Level 1 — Recognition

Recall Solution 1.1

Straight from the family table:

M0+ — $N = 2$ stages, no FPU.
M3 — $N = 3$ stages, no FPU.
M4 — $N = 3$ stages, FPU optional (only on the "M4F" variant), and if present it is single-precision only.
M7 — $N = 6$ stages (dual-issue), FPU optional, and can be single + double precision.

Why "by default" matters: even on an M4F/M7 the FPU is off at reset — you must set the CP10/CP11 bits in CPACR first (see Exercise 5.2).

Recall Solution 1.2

The NVIC (Nested Vectored Interrupt Controller). On an interrupt it automatically:

Pushes 8 registers (R0–R3, R12, LR, PC, xPSR) onto the current stack, and
Looks up the handler address in the vector table and jumps straight to it.

Both happen in a fixed, known number of cycles — that fixed-ness (not zero, but knowable) is what makes timing deterministic. See Interrupts and the NVIC.

Level 2 — Application

Recall Solution 2.1

What/why: use the pipeline-fill formula because we count cycles for a straight run of instructions. $Cycles = (N - 1) + I = (2 - 1) + 50 = 51 .$ The pipe costs 1 extra cycle to fill (only 1 stage beyond the first), then 50 instructions stream out one per cycle.

Recall Solution 2.2

Cycles: $(3 - 1) + 10 = 12$ cycles. Time: $t = 12/168 = 0.0714 μ s$ . Since $1 μ s = 1000 ns$ , that is $0.0714 \times 1000 \approx 71.4 ns$ . Why divide by 168: each cycle lasts $1/168 μ s$ , and we have 12 of them.

Recall Solution 2.3

The key insight: across iterations the pipe stays full, so you pay the fill cost once, not per loop. $I_{total} = 1000 \times 10 = 10, 000, Cycles = (3 - 1) + 10, 000 = 10, 002 .$ Not $1000 \times 12 = 12, 000$ — that would wrongly re-fill the pipe every pass. The back-edge edge case, stated plainly: the loop's conditional branch is already inside the 10 instructions (it is counted in $I$ ), and because we assume perfect branch prediction it costs its normal one cycle with no flush. If, instead, the back-edge mispredicted even once per pass, you would add $(N - 1) = 2$ flush cycles per pass, giving $10, 002 + 1000 \times 2 = 12, 002$ cycles. So loop overhead is either "free-ish" (predicted) or a per-pass $(N - 1)$ tax (mispredicted) — never silently ignored.

Recall Solution 2.4

$IPC = 1 + p (w - 1) = 1 + 0.4 (2 - 1) = 1.4.$ Cycles $\approx I / IPC = 10, 000/1.4 = 7142.86 \to 7143$ cycles (round up — you can't run a partial cycle). Why divide: IPC is instructions per cycle, so cycles = instructions ÷ IPC.

Level 3 — Analysis

Recall Solution 3.1

(a) M3: $32 \times 2 = 64$ cycles/sample.
(b) M4 MLA: $32 \times 1 = 32$ cycles/sample.
(c) M4 SMLAD: two MACs per instruction $\Rightarrow 32/2 = 16$ cycles/sample.
Speedup M3 → SMLAD: $64/16 = 4 \times$ — and this is per MHz, before the M4's higher clock helps further.

Why SIMD halves it: one 32-bit instruction operates on two packed 16-bit lanes at once (the blue and yellow lanes in the figure above). See Fixed-point vs floating-point DSP.

Recall Solution 3.2

M3 soft-float: $5 \times 40 = 200$ cycles.
M4F hardware: $5 \times 2 = 10$ cycles.
Ratio: $200/10 = 20 \times$ faster.
double trap: the M4 FPU is single-precision only, so every double op silently falls back to software emulation — you're back near the 200-cycle regime. Use float literals (3.14f) and sinf, not sin.

Recall Solution 3.3

$L_{max} = 2 + 12 + 30 = 44 cycles .$ $t = 44/100 = 0.44 μ s .$ Since $1 μ s = 1000 ns$ , that is $0.44 \times 1000 = 440 ns$ . Why each term is bounded: detect is one sync stage, stack is a fixed 12-cycle push, and the blocking term is bounded because you know the longest higher-priority handler. Determinism = every term knowable, not zero.

Level 4 — Synthesis

Recall Solution 4.1

Cycles per sample: $64 \times 0.5 = 32$ cycles. Deadline per sample: $1/48000 s = 20.83 μ s$ . Required clock: we need $32$ cycles to fit in $20.83 μ s$ , so $f \geq \frac{32 cycles}{20.83 μ s} = 1.536 MHz .$ So even a modest ~2 MHz clock technically meets it — meaning the FIR is not the bottleneck; interrupts and other tasks dominate. (Real designs still pick ~100 MHz for headroom against jitter and other tasks. See RTOS task scheduling and context switching.)

Recall Solution 4.2

Cycles/second in switching: $120 \times 1000 = 120, 000$ cycles/s. Cycles/second available: $72 \times 1 0^{6}$ . Fraction: $120, 000/72, 000, 000 = 0.001 \overline{6} = 0.167%$ . Tiny — which is why the auto-stacking NVIC + two-stack (MSP/PSP) design is so valued: switching overhead stays negligible. See RTOS task scheduling and context switching.

Recall Solution 4.3

FFT / image stream → cacheable main memory. It benefits from cache hits and its timing only needs to be good on average, not worst-case-guaranteed.
Servo loop code + data → TCM (tightly-coupled memory). TCM has single-cycle, fixed access with no cache misses, so its worst-case timing is bounded — exactly what a hard 10 µs deadline needs.

Why not cache the servo? Because a cache miss makes access time data-dependent: a hit is fast, but a miss stalls the core for many cycles while it fetches from slow main memory. That variability means you can no longer prove the servo finishes within 10 µs in the worst case — and hard-real-time is judged on the worst case, never the average. TCM removes the gamble entirely: every access is a fixed single cycle, so the deadline is provable. Rule of thumb: determinism > average speed for anything with a hard deadline. See Cache vs TCM in real-time systems.

Level 5 — Mastery

Recall Solution 5.1

Design A: single-issue ⇒ IPC $= 1$ , so $\approx 100, 000$ cycles. $t_{A} = 100, 000/120 MHz = 833.33 μ s .$ Design B: $IPC = 1 + 0.35 (2 - 1) = 1.35$ , so cycles $= 100, 000/1.35 = 74, 074.07 \to 74, 075$ cycles. $t_{B} = 74, 074.07/300 = 246.91 μ s .$ Speedup: $t_{A} / t_{B} = 833.33/246.91 = 3.375 \times$ . Notice the win splits into two independent factors: clock ( $300/120 = 2.5 \times$ ) and IPC ( $1.35 \times$ ), and $2.5 \times 1.35 = 3.375$ . Depth alone bought the clock; dual-issue bought the extra 1.35.

Recall Solution 5.2

Cause: the FPU is a coprocessor (CP10/CP11) that is disabled at reset. Your compiled code emitted real hardware FP instructions (because of -mfloat-abi=hard), but with the coprocessor disabled those instructions are undefined and trap as a HardFault. Fix: in SystemInit (startup) set the CP10/CP11 access bits in the CPACR register — commonly: SCB->CPACR |= (0xF << 20); (grants full access to CP10 and CP11), then a DSB/ISB barrier. No arithmetic here, but it's the single most common "my float crashes" mystery.

Recall Solution 5.3

Does the stacking get wasted? No. Cortex-M uses late-arrival: when a higher-priority IRQ appears during the stacking already in progress, the CPU reuses that same register push and simply vectors to the higher-priority handler — it does not push a second time. So we count the stacking once, not twice.

Walk the timeline in order:

detect the pending interrupt: $2$ cycles.
stack the 8 registers (shared, done exactly once thanks to late-arrival): $12$ cycles.
high-priority handler body runs to completion: $20$ cycles.
exception-return / unstack path before the servo body starts: $12$ cycles.

$L = 2 + 12 + 20 + 12 = 46 cycles .$ $t = \frac{46}{80} = 0.575 μ s .$ Since $1 μ s = 1000 ns$ , that is $0.575 \times 1000 = 575 ns$ .

The mastery point: the naive answer double-counts the push as $2 + 12 + 12 + 20 + 12 = 58$ cycles. Late-arrival (and its sibling tail-chaining) is exactly the hardware mechanism that removes that duplicate 12-cycle push, keeping worst-case latency bounded and knowable even under nested preemption. See Interrupts and the NVIC.

Recall Self-test checklist (reveal after finishing)

Pipeline fill paid once per run? ::: Yes — add $(N - 1)$ a single time, not per loop (assuming no branch flushes). IPC formula direction? ::: Cycles = Instructions ÷ IPC (IPC is instructions per cycle). double on M4F? ::: Software emulation — slow. Single-precision float only in hardware. Cycles → time? ::: Divide cycles by clock in MHz to get µs; multiply µs by 1000 to read ns. Nested IRQ stacking counted how many times? ::: Once (tail-chain / late-arrival reuse), not per level. What breaks the ideal $(N - 1) + I$ ? ::: Branch mispredictions, data/memory stalls, exceptions — each adds a re-fill/bubble penalty.