Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7): Exercises

5.5.1 · D4 · Coding › Embedded Systems & Real-Time Software › Microcontroller architecture — ARM Cortex-M series (M0, M3,

Intuition Is page ko kaise use karein

Solution callout ko cover karo, problem ko cold try karo, phir reveal karo. Levels waise hi climb karte hain jaise cores ka ladder hai: pehle tum sirf ek spec ko recognise karte ho, phir pipeline/latency formulas apply karte ho, phir trade-offs analyse karte ho, phir ek design synthesise karte ho, phir ek nasty edge case master karte ho. Is page par har numeric answer machine-checked hai — verification block dekhो jo is note ke saath ship hota hai (har exercise ka number sympy mein re-derive hota hai). Agar tumhara answer kisi checked answer se disagree kare, toh check par trust karo aur apni galti dhundho.

Prerequisites jo tum open rakhna chahoge: the parent topic, Pipelining and superscalar execution, Interrupts and the NVIC, RTOS task scheduling and context switching, Fixed-point vs floating-point DSP, IEEE-754 floating point, Cache vs TCM in real-time systems, Memory-mapped I/O and GPIO, Memory Protection Unit (MPU).

Shuru karne se pehle, chalte hain un teen formulas ko re-earn karte hain jin par hum rely karenge, taaki koi bhi symbol bina explanation ke na aaye.

Formula Teen tools jo hum baar baar use karte hain

1. Pipeline fill. Ek $N$ -stage pipeline ek assembly line hai jisme $N$ work-stations hain. Pehli instruction ko exit hone se pehle saare $N$ stations se guzarna padta hai — uski cost $N$ cycles hoti hai. Uske baad, har cycle mein ek nayi instruction exit hoti hai. Toh $I$ instructions lete hain $Cycles = (N - 1) + I .$ Yahan $N$ = pipeline stages ki sankhya (ek whole number), $I$ = run ki gayi instructions ki sankhya (ek whole number), aur ek cycle CPU clock ki ek tick hai.

2. Superscalar IPC. "Issue width" $w$ = core kitni instructions ek cycle mein launch kar sakta hai. "Pairing fraction" $p$ = wo fraction ( $0$ aur $1$ ke beech) jo actually ek partner dhundh leti hai saath launch hone ke liye. Tab instructions-per-cycle hota hai $IPC = 1 + p (w - 1) .$ Yeh formula kyun? Socho instructions single file mein march kar rahe hain: ek akeli instruction hamesha IPC $= 1$ deti hai (ek per cycle). Ab, jab bhi ek instruction pair up karti hai, toh woh $(w - 1)$ extra doston ko usi cycle mein saath kheench leti hai bilkul free mein — lekin yeh bonus sirf us fraction $p$ ke liye hota hai jo pair manage karti hain. Toh har instruction ka average bonus hai $p (w - 1)$ , aur tum ise baseline $1$ mein add karte ho: $IPC = 1 + p (w - 1)$ . (Ends check karo: $p = 0$ → koi pairing nahi → IPC $= 1$ ; $p = 1$ , $w = 2$ → sab pair → IPC $= 2$ , matlab har cycle mein double kaam.) IPC literally matlab: average mein, har clock tick mein kitni instructions finish hoti hain.

3. Cycles se Time. $f$ MHz par ek clock $f$ million times per second tick karta hai, toh ek cycle $1/ f$ microseconds tak rehta hai: $t = \frac{Cycles}{f ( MHz )} μ s .$ ( $μ s$ = microsecond = ek millionth of a second. Kabhi kabhi hum aur zoom in karenge $ns$ = nanosecond = ek billionth of a second, toh $1 μ s = 1000 ns$ — sirf µs answer ko 1000 se multiply karo ns mein padhne ke liye.)

Neecha wali picture exactly dikhati hai kyun pipeline-fill formula $(N - 1) + I$ hai aur $N \times I$ nahi — ise Level 2 se pehle padho.

Figure — Microcontroller architecture — ARM Cortex-M series (M0, M3, M4, M7)

Common mistake Reality check: jab

$(N - 1) + I$ exactly hold nahi karta Kyun sahi lagta hai: assembly-line picture itni clean hai ki lagta hai pipe hamesha full hoti hai. Sach yeh hai: formula assume karta hai koi stalls nahi. Real code mein staircase in par toot jaata hai:

ek branch misprediction — CPU ne galat next instruction guess ki, toh use partially-filled pipe ko flush karna padta hai aur re-fill karna padta hai, roughly $(N - 1)$ cycles har baar ka cost. Deep pipes (M7's 6 stages) yahan M0+'s 2 stages se zyada hurt karte hain.
ek data hazard / memory stall — ek instruction ko ek result (ya slow memory word) chahiye jo ready nahi hai, toh pipe stall ho jaata hai (bubbles insert hote hain).
ek interrupt/exception — control jump ho jaata hai aur pipe handler par re-fill hoti hai. Fix: $(N - 1) + I$ ko ideal (no-stall) count ke roop mein use karo, phir add karo per-event penalties. Har exercise yahan "no stalls" isliye kehta hai taaki ideal formula apply ho — lekin worst-case real-time budgets mein flush terms wapas add karne chahiye.

Level 1 — Recognition

Recall Solution 1.1

Seedha family table se:

M0+ — $N = 2$ stages, koi FPU nahi.
M3 — $N = 3$ stages, koi FPU nahi.
M4 — $N = 3$ stages, FPU optional (sirf "M4F" variant par), aur agar present hai toh yeh single-precision only hai.
M7 — $N = 6$ stages (dual-issue), FPU optional, aur ho sakta hai single + double precision.

"By default" kyun matter karta hai: M4F/M7 par bhi FPU reset par off hota hai — tumhe pehle CPACR mein CP10/CP11 bits set karne honge (Exercise 5.2 dekhо).

Recall Solution 1.2

NVIC (Nested Vectored Interrupt Controller). Interrupt par yeh automatically:

8 registers push karta hai (R0–R3, R12, LR, PC, xPSR) current stack par, aur
Handler address look up karta hai vector table mein aur seedha wahan jump karta hai.

Dono ek fixed, known number of cycles mein hote hain — woh fixed-ness (zero nahi, lekin knowable) hi timing ko deterministic banata hai. Dekhо Interrupts and the NVIC.

Level 2 — Application

Recall Solution 2.1

Kya/kyun: pipeline-fill formula use karo kyunki hum cycles count kar rahe hain ek straight run of instructions ke liye. $Cycles = (N - 1) + I = (2 - 1) + 50 = 51 .$ Pipe ko fill karne ke liye 1 extra cycle lagti hai (pehle ke baad sirf 1 stage), phir 50 instructions ek cycle mein stream out hoti hain.

Recall Solution 2.2

Cycles: $(3 - 1) + 10 = 12$ cycles. Time: $t = 12/168 = 0.0714 μ s$ . Kyunki $1 μ s = 1000 ns$ , woh hai $0.0714 \times 1000 \approx 71.4 ns$ . 168 se kyun divide karein: har cycle $1/168 μ s$ tak rehti hai, aur humare paas unki 12 hain.

Recall Solution 2.3

Key insight: iterations ke across pipe full rehti hai, toh tum fill cost ek baar pay karte ho, har loop par nahi. $I_{total} = 1000 \times 10 = 10, 000, Cycles = (3 - 1) + 10, 000 = 10, 002 .$ Nahi $1000 \times 12 = 12, 000$ — woh galat hoga, pipe har pass re-fill hogi. Back-edge edge case, clearly stated: loop ki conditional branch pehle se un 10 instructions mein hai (woh $I$ mein counted hai), aur kyunki hum perfect branch prediction assume karte hain woh back-edge branch apna normal ek cycle cost karti hai bina flush ke. Agar, instead, back-edge har pass mein ek baar bhi mispredict kare, toh tum add karte $(N - 1) = 2$ flush cycles per pass, dete $10, 002 + 1000 \times 2 = 12, 002$ cycles. Toh loop overhead ya toh "free-ish" hai (predicted) ya ek per-pass $(N - 1)$ tax (mispredicted) — kabhi silently ignore nahi hoti.

Recall Solution 2.4

$IPC = 1 + p (w - 1) = 1 + 0.4 (2 - 1) = 1.4.$ Cycles $\approx I / IPC = 10, 000/1.4 = 7142.86 \to 7143$ cycles (round up — partial cycle nahi ho sakti). Kyun divide karein: IPC matlab instructions per cycle, toh cycles = instructions ÷ IPC.

Level 3 — Analysis

Recall Solution 3.1

(a) M3: $32 \times 2 = 64$ cycles/sample.
(b) M4 MLA: $32 \times 1 = 32$ cycles/sample.
(c) M4 SMLAD: do MACs per instruction $\Rightarrow 32/2 = 16$ cycles/sample.
Speedup M3 → SMLAD: $64/16 = 4 \times$ — aur yeh per MHz hai, M4 ke higher clock se pehle jo aur help karta hai.

SIMD kyun half karta hai: ek 32-bit instruction do packed 16-bit lanes par ek saath operate karta hai (figure mein blue aur yellow lanes). Dekhо Fixed-point vs floating-point DSP.

Recall Solution 3.2

M3 soft-float: $5 \times 40 = 200$ cycles.
M4F hardware: $5 \times 2 = 10$ cycles.
Ratio: $200/10 = 20 \times$ faster.
double trap: M4 FPU single-precision only hai, toh har double op silently software emulation par fall back karta hai — tum wapas near 200-cycle regime mein ho. float literals (3.14f) aur sinf use karo, sin nahi.

Recall Solution 3.3

$L_{max} = 2 + 12 + 30 = 44 cycles .$ $t = 44/100 = 0.44 μ s .$ Kyunki $1 μ s = 1000 ns$ , woh hai $0.44 \times 1000 = 440 ns$ . Har term kyun bounded hai: detect ek sync stage hai, stack ek fixed 12-cycle push hai, aur blocking term isliye bounded hai kyunki tum jaante ho longest higher-priority handler kya hai. Determinism = har term knowable, zero nahi.

Level 4 — Synthesis

Recall Solution 4.1

Cycles per sample: $64 \times 0.5 = 32$ cycles. Deadline per sample: $1/48000 s = 20.83 μ s$ . Required clock: hume $32$ cycles ko $20.83 μ s$ mein fit karna hai, toh $f \geq \frac{32 cycles}{20.83 μ s} = 1.536 MHz .$ Toh ek modest ~2 MHz clock bhi technically isko meet karta hai — matlab FIR bottleneck nahi hai; interrupts aur dusre tasks dominate karte hain. (Real designs phir bhi ~100 MHz pick karte hain jitter aur dusre tasks ke against headroom ke liye. Dekhо RTOS task scheduling and context switching.)

Recall Solution 4.2

Cycles/second switching mein: $120 \times 1000 = 120, 000$ cycles/s. Cycles/second available: $72 \times 1 0^{6}$ . Fraction: $120, 000/72, 000, 000 = 0.001 \overline{6} = 0.167%$ . Tiny — yahi wajah hai ki auto-stacking NVIC + two-stack (MSP/PSP) design itna valued hai: switching overhead negligible rehta hai. Dekhо RTOS task scheduling and context switching.

Recall Solution 4.3

FFT / image stream → cacheable main memory. Yeh cache hits se benefit karta hai aur iski timing sirf on average good honi chahiye, worst-case-guaranteed nahi.
Servo loop code + data → TCM (tightly-coupled memory). TCM mein single-cycle, fixed access hoti hai koi cache misses nahi, toh uski worst-case timing bounded hoti hai — exactly wahi jo hard 10 µs deadline ko chahiye.

Servo ko cache kyun nahi karein? Kyunki ek cache miss access time ko data-dependent banata hai: ek hit fast hota hai, lekin ek miss core ko kai cycles ke liye stall karta hai jab woh slow main memory se fetch karta hai. Woh variability matlab hai tum ab prove nahi kar sakte ki servo worst case mein 10 µs ke andar finish hoga — aur hard-real-time worst case par judge hota hai, average par kabhi nahi. TCM poora gamble hata deta hai: har access ek fixed single cycle hai, toh deadline provable hai. Rule of thumb: deadline wali cheez ke liye determinism > average speed. Dekhо Cache vs TCM in real-time systems.

Level 5 — Mastery

Recall Solution 5.1

Design A: single-issue ⇒ IPC $= 1$ , toh $\approx 100, 000$ cycles. $t_{A} = 100, 000/120 MHz = 833.33 μ s .$ Design B: $IPC = 1 + 0.35 (2 - 1) = 1.35$ , toh cycles $= 100, 000/1.35 = 74, 074.07 \to 74, 075$ cycles. $t_{B} = 74, 074.07/300 = 246.91 μ s .$ Speedup: $t_{A} / t_{B} = 833.33/246.91 = 3.375 \times$ . Notice karo ki win do independent factors mein split hota hai: clock ( $300/120 = 2.5 \times$ ) aur IPC ( $1.35 \times$ ), aur $2.5 \times 1.35 = 3.375$ . Depth akele ne clock buy kiya; dual-issue ne extra 1.35 buy kiya.

Recall Solution 5.2

Cause: FPU ek coprocessor (CP10/CP11) hai jo reset par disabled hota hai. Tumhara compiled code real hardware FP instructions emit karta hai (kyunki -mfloat-abi=hard hai), lekin coprocessor disabled hone ke saath woh instructions undefined hain aur HardFault ke roop mein trap ho jaati hain. Fix: SystemInit (startup) mein CPACR register mein CP10/CP11 access bits set karo — commonly: SCB->CPACR |= (0xF << 20); (CP10 aur CP11 ko full access deta hai), phir ek DSB/ISB barrier. Yahan koi arithmetic nahi, lekin yeh sabse common "meri float crash karti hai" mystery hai.

Recall Solution 5.3

Kya stacking wasted hoti hai? Nahi. Cortex-M late-arrival use karta hai: jab stacking ke dauraan ek higher-priority IRQ appear hota hai, CPU woh same register push reuse karta hai aur simply higher-priority handler par vector karta hai — woh second time push nahi karta. Toh hum stacking ek baar count karte hain, do baar nahi.

Timeline ko order mein walk karo:

Pending interrupt ko detect karo: $2$ cycles.
8 registers stack karo (shared, exactly once done late-arrival ki wajah se): $12$ cycles.
High-priority handler body completion tak run karta hai: $20$ cycles.
Exception-return / unstack path servo body start hone se pehle: $12$ cycles.

$L = 2 + 12 + 20 + 12 = 46 cycles .$ $t = \frac{46}{80} = 0.575 μ s .$ Kyunki $1 μ s = 1000 ns$ , woh hai $0.575 \times 1000 = 575 ns$ .

Mastery point: naive answer push ko double count karta hai jaise $2 + 12 + 12 + 20 + 12 = 58$ cycles. Late-arrival (aur uska sibling tail-chaining) exactly woh hardware mechanism hai jo duplicate 12-cycle push remove karta hai, worst-case latency ko bounded aur knowable rakhta hai nested preemption ke under bhi. Dekhо Interrupts and the NVIC.

Recall Self-test checklist (finish karne ke baad reveal karo)

Pipeline fill ek baar paid per run? ::: Haan — $(N - 1)$ ek baar add karo, har loop nahi (assume karo koi branch flushes nahi). IPC formula direction? ::: Cycles = Instructions ÷ IPC (IPC matlab instructions per cycle). M4F par double? ::: Software emulation — slow. Sirf single-precision float hardware mein. Cycles → time? ::: Cycles ko clock in MHz se divide karo µs paane ke liye; µs ko 1000 se multiply karo ns mein padhne ke liye. Nested IRQ stacking kitni baar count hoti hai? ::: Ek baar (tail-chain / late-arrival reuse), har level par nahi. Ideal $(N - 1) + I$ kya break karta hai? ::: Branch mispredictions, data/memory stalls, exceptions — har ek re-fill/bubble penalty add karta hai.