Dark silicon problem: Visual walkthrough — Hinglish deep dive

6.4.7 · D2 · Hardware › Power, Thermal & Reliability › Dark silicon problem

Step 1 — "Power" ka matlab ek transistor ke liye kya hota hai

KYA HAI. Ek transistor ek chhota sa switch hota hai. Har baar jab woh OFF se ON hota hai, ek chhote se bucket mein electric charge bharta hai, aur jab woh wapis flip hota hai toh woh charge heat ke roop mein dump ho jaata hai. In flips ki ginti per second, times har dump ka size, wahi power hai — energy burned per second, jo watts (W) mein measure hoti hai.

PEHLE YE KYUN. Dark silicon ek heat problem hai. Isse pehle ki hum keh sakein ki chip itni garm kyun hoti hai, humein ek switch ki heat count karni chahiye. Baaki sab isi ki bahut saari copies hain.

PICTURE. Picture dekho: magenta capacitor "bucket" ek height tak bharta hai jo supply voltage $V$ se set hoti hai (kitna hard hum charge push karte hain), aur woh $f$ baar har second empty hota hai (clock frequency). Ek fill ka area $C V^{2}$ ke proportional hai — bucket ki width $C$ times fill ki energy $V^{2}$ .

$V^{2}$ kyun, $V$ kyun nahi? Ek charged bucket mein stored energy $\frac{1}{2} C V^{2}$ hoti hai — double push karo aur tum chaar guna energy store karte ho, sirf double nahi. Wahi quadratic hai jis wajah se voltage sabse powerful knob hai hamare paas.

Step 2 — Power per unit area: woh crowding jo actually burn karti hai

KYA HAI. Ek transistor ke watts harmless hain. Ek billion ko ek fingernail-sized square mein pack karna nahi hai. Jo chip ko melt karta hai woh hai power density — watts divided by area $A$ .

KYUN. Ek cooler sirf itne hi watts pull kar sakta hai har square millimetre se. Toh jo quantity physics care karti hai woh total power nahi hai, woh power per area hai.

PICTURE. Do identical chips, same total watts (same total orange glow), lekin right wali ek-chauthai area mein pack hai — glow per square chaar guna bright hai, aur wahi heatsink feel karta hai.

Step 3 — Dennard ka magic: kyun shrinking pehle free hoti thi

KYA HAI. 1974 se lekar 2005 tak, har naye "node" mein har transistor ki length factor $s$ se shrink hoti thi (maan lo $s = 1.4$ ). Dennard ka rule kehta tha: voltage aur capacitance ko bhi usi $s$ se shrink karo, aur frequency ko $s$ se rise karne do. Ab hum track karte hain ki yeh power density ko kya karta hai.

YEH STEP KYUN. Hum purani duniya ko perfectly kaam karte dekhen, taaki Step 4 mein jab woh toot-ti hai toh damage obvious ho. Yeh "before" photo hai.

PICTURE. Arrow par table: har quantity apna $s$ -factor carry karti hai. Dekho har $s$ cancel ho jaata hai.

Result: double transistors, same temperature. Tees saalon tak, zyada matlab free tha. Dekho Dennard-scaling.

Step 4 — The break: $V$ ek floor tak pahunch jaata hai

KYA HAI. 65 nm ke aaspaas voltage $V$ shrink hona band ho gaya. Ek transistor tab ON hota hai jab $V$ ek fixed threshold voltage $V_{t}$ se meaningfully upar uthta hai — woh minimum push jo switch kholne ke liye chahiye. $V_{t}$ barely scale hota hai, toh jab $V$ $\sim 0.7 V$ ke paas aaya toh woh aur neeche nahi ja sakta bina switch fail hue.

YEH KYUN MATTER KARTA HAI. Agar $V$ stuck hai lekin hum phir bhi $f$ ko har generation mein $s$ se badhate hain, toh Step 3 ko $V$ frozen karke phir se run karo — voltage se aane wala $\frac{1}{s ^{2}}$ gone hai.

PICTURE. Violet "voltage floor" line: pehle ke nodes freely neeche slide karte hain; 65 nm se dots floor par pile up ho jaate hain aur descend nahi kar sakte. Leakage (orange seep-through jab bhi OFF ho) badhti hai jab insulation atom-thin ho jaata hai.

Plus ek aur leak: jab oxide kuch atoms tak thin ho jaata hai, electrons directly tunnel karte hain chahe switch OFF ho, jis se static (leakage) power $P_{static} = V I_{leak}$ milti hai jo fast grow karti hai.

Step 5 — The wall: ek fixed power budget (TDP)

KYA HAI. Ek cooler maximum itne fixed watts remove kar sakta hai. Manufacturers is ceiling ko Thermal Design Power, $P_{TDP}$ , ke roop mein publish karte hain. $P_{TDP}$ se zyada draw karo aur chip overheat ho jaati hai. Yeh transistor count ke saath grow nahi karta.

KYUN. Yeh ceiling woh wall hai jis mein growing power density takraati hai. Transistors saste hain (Moore's Law, Mores-law); unhe run karne ke watts rationed hain (dekho TDP-and-power-budget).

PICTURE. Ek rising staircase (total power jo saare cores chahte hain, har node mein doubling) ek flat navy ceiling (TDP) se cap hoti hai. Ceiling ke upar sab kuch forbidden hai.

Step 6 — Jinhe hum light kar sakte hain un cores ko count karna

KYA HAI. Budget ko cores mein divide karo. Har core $P_{core}$ watts cost karti hai; tumhare paas spend karne ke liye $P_{TDP}$ hai. Jinhe tum on kar sakte ho unki ginti budget divided by price hai, down rounded (tum aadhi core nahi run kar sakte).

FLOOR KYUN. $⌊ x ⌋$ (floor function) ka matlab hai "fractional part throw away karo." Agar budget $8.7$ cores buy karta hai, tum $8$ light kar sakte ho — $0.7$ nauveen pure core ke liye enough nahi hai.

PICTURE. $N$ core-tiles ki ek row; ek magenta budget bar tiles ko left-to-right fill karta hai jab tak paisa khatam na ho jaaye. Lit tiles glow karti hain; baaki dark violet rehti hain.

Step 7 — Dark fraction, assembled

KYA HAI. Fraction dark woh leftover share hai total wanted-power ka jo budget cover nahi kar saka.

KYUN. Utilization = jo hum power kar sakte hain ÷ jo hum chahna chahte hain $= \frac{P _{TDP}}{N P _{core}}$ . Dark simply woh sab hai jo utilized nahi hai: ek minus woh.

PICTURE. Area $N P_{core}$ ka ek full pie. Magenta slice powered part $P_{TDP}$ hai; violet rest dark hai. Uska angle wahi dark fraction hai.

Worked check (parent table ki 2015 row). $N = 32$ , $P_{TDP} = 100$ W, $P_{core} = 12.5$ W: $Active = ⌊ \frac{100}{12.5} ⌋ = 8, Dark = 1 - \frac{100}{32 \cdot 12.5} = 1 - \frac{100}{400} = 0.75 = 75%.$

Step 8 — Har edge case (taaki tumhe koi unseen case na mile)

KYA HAI & KYUN. Formula ko apni extremes par sahi behave karna chahiye; yahan saare chaar corners hain.

PICTURE. Chaar mini-pies: generous budget, tight budget, leakage caveat, aur DVFS rescue.

Ek-picture summary

Yahan poori chain ek canvas par hai: ek transistor ka $α C V^{2} f$ (Step 1) → area par density (Step 2) → Dennard ka $s$ -cancellation (Step 3) → $V$ -floor use $s^{2}$ growth mein todna (Step 4) → flat TDP ceiling (Step 5) → active cores mein floor-divide (Step 6) → dark-fraction pie (Step 7).

Recall Feynman retelling — plain words mein wapas bolo

Chip par har chhota switch heat burn karta hai jo kitna hard hum use push karte hain, squared, times kitni jaldi woh flip karta hai, ke proportional hai. Zyada switches kam space mein pack karo aur heat per square badh jaati hai. Tees saalon tak ek magic trick jise Dennard scaling kehte hain heat-per-square ko constant rakhti thi: har shrink mein voltage itna neeche aata tha ki crowding cancel ho jaaye. Phir voltage ek floor par aa gaya teeen-chauthai volt ke aaspaas — ussse neeche switches on nahi honge — toh trick khatam ho gayi. Ab har shrink chip ko aur garm karta hai. Lekin cooler sirf itne fixed watts carry off kar sakta hai (TDP). Toh hum woh fixed budget lete hain, ek core ki cost se divide karte hain, aur wahi hain kitne cores hum light kar sakte hain — rounded down. Baaki dark rehne chahiye. Dark mein chhoda gaya share ek minus hai (budget over total wanted power). Jab hum transistors double karte rehte hain ek frozen budget ke saath, woh dark share 100% ki taraf creep karta hai. Yeh truly free nahi hai, kyunki off transistors phir bhi leak karte hain. Hamare escapes hain sab kuch slower aur cooler run karna (DVFS), power completely cut karna (power gating), aur specialized cores banana jo zyada kaam karte hain per watt.

Recall Quick self-test

Frozen voltage density growth ko constant se $s^{2}$ mein kyun change karta hai? ::: $V$ fixed hone ke saath, woh $\frac{1}{s ^{2}}$ jo voltage-squared contribute karta tha woh gone hai; surviving $\frac{1}{s}$ (capacitance) aur $s$ (frequency) galat jagah $s^{2} / s^{2}$ chhodte hain, toh density $s^{2}$ ki tarah scale hoti hai. Ek chip mein $N = 16$ , TDP $= 40$ W, $P_{core} = 8$ W hai. Active cores aur dark fraction? ::: Active $= ⌊ 40/8 ⌋ = 5$ ; dark $= 1 - 40/ (16 \cdot 8) = 1 - 40/128 = 0.6875 = 68.75%$ . Active cores count karte waqt down kyun round karte hain? ::: Tum fractional core power nahi kar sakte; leftover budget jo ek whole core ke liye enough nahi hai woh waste ho jaata hai, toh floor function use karo.