PCIe lanes, links, and bandwidth: Worked examples — Hardware deep dive

This page is the drill ground for PCIe lanes, links, and bandwidth. The parent note built the six-step bandwidth formula from raw signalling rate to full-duplex aggregate. Here we take that machine and feed it every kind of input it can ever meet — big lanes, tiny lanes, mismatched generations, the number zero, a bifurcated slot, a word problem, and an exam trap — so no scenario ever surprises you.

Before the examples we lay out a map of all the cases. Every worked example below is stamped with the map-cell it covers, so you can see that nothing is left uncovered.

The one formula everything comes from

Everything on this page is one chain. Let us name each piece in plain words first, so no symbol appears unearned.

Why this tool and not, say, adding the rates? Because the four effects are independent multipliers, not additions. Halving lanes and halving efficiency each cut the result by the same proportion, so they multiply. Addition would mix units (GT/s + lanes is meaningless).

The scenario matrix

Below is every class of input this topic can throw at you. Each row is a distinct "shape" of problem; the last column names the example that pins it down.

Cell	Case class	What is being stressed	Covered by
A	Plain forward calc (one gen, one width)	The core chain, no traps	Example 1
B	Byte↔bit / MB↔GB unit gymnastics	Converting between the units marketers use	Example 2
C	Mismatched generation and width (negotiated down)	Two things wrong at once	Example 3
D	Bifurcation split (one slot → two links)	Dividing lanes, conserving total	Example 4
E	Full-duplex aggregate vs one-way	The ×2 trap	Example 5
F	Zero / degenerate input ( $N = 0$ , disconnected, x1)	Edge & smallest cases	Example 6
G	Reverse solve (given BW, find lanes)	Running the chain backwards	Example 7
H	Real-world word problem (bottleneck reasoning)	Which link is the limit?	Example 8
I	Exam-style twist (per-lane Gen numbers hidden)	Reading the trap in the wording	Example 9

The reference numbers we keep reusing (all one-direction, from the parent's master table):

Gen	$R$ (GT/s)	$η$	Per-lane GB/s
1.0	2.5	0.8	0.250
2.0	5.0	0.8	0.500
3.0	8.0	128/130	0.985
4.0	16.0	128/130	1.969
5.0	32.0	128/130	3.938

Worked examples

Worked example Example 1 — Cell A: the plain forward calc

Statement. What is the one-way bandwidth of a PCIe 3.0 x8 link?

Forecast: guess now — is it above or below 8 GB/s? Write it down.

Pick the numbers: Gen 3.0 → $R = 8.0$ GT/s, $η = \frac{128}{130}$ . Why this step? The chain needs $R$ and $η$ ; both are fixed by the generation, not the width.
Per-lane data rate in bits: $8.0 \times \frac{128}{130} = 7.877$ Gbps. Why this step? $R \times η$ strips out encoding overhead, leaving payload bits/s.
Per-lane in bytes: $7.877/8 = 0.985$ GB/s. Why this step? Divide by 8 because a byte is 8 bits — pure unit change.
Scale by width: $N = 8$ → $8 \times 0.985 = 7.877$ GB/s. Why this step? Lanes are parallel and independent, so bandwidth scales linearly.

Answer: ≈ 7.88 GB/s (one way).

Verify: Units: $GT/s \times (unitless) \times lanes \times \frac{1}{8}$ = GB/s ✓. Sanity: x8 is half of x16, and Gen 3.0 x16 is 15.75 GB/s from the table; half of that is 7.88 ✓.

Worked example Example 2 — Cell B: unit gymnastics

Statement. A datasheet says "984 MB/s per lane, Gen 3.0." Is that the same lane rate we computed?

Forecast: MB/s vs GB/s — will the numbers match or be off by 1000?

Our lane rate was $0.985$ GB/s. Convert to MB/s. Why this step? The datasheet uses megabytes; we must use the same unit before comparing.
In PCIe land $1 GB/s = 1000 MB/s$ (decimal, powers of ten — not 1024). Why this step? PCIe throughput is quoted in SI decimal units, so no $2^{10}$ factor sneaks in.
$0.985 GB/s \times 1000 = 985 MB/s$ . Why this step? Straight multiply to change the prefix.

Answer: Datasheet's 984 vs our 985 — a 1 MB/s rounding gap. Same number.

Verify: Round-trip: $985/1000 = 0.985$ GB/s, back to where we started ✓. If we had wrongly used 1024, we'd get $0.985 \times 1024 = 1008$ MB/s — clearly not what the sheet says, confirming decimal is correct.

Worked example Example 3 — Cell C: two things wrong at once

Statement. A GPU meant for PCIe 4.0 x16 got seated in a slot that negotiates PCIe 3.0 x4. What one-way bandwidth remains, and what fraction of intended is that? (See Motherboard Lane Allocation.)

Forecast: more than half lost, or less? Commit.

Intended: Gen 4.0 x16 → $16 \times 1.969 = 31.51$ GB/s. Why this step? This is the target we compare against.
Actual: Gen 3.0 x4 → $4 \times 0.985 = 3.94$ GB/s. Why this step? Both knobs changed: lower $R, η$ (Gen 3 not 4) and fewer lanes (4 not 16). We must apply both.
Fraction kept: $3.94/31.51 = 0.125 = 12.5%$ . Why this step? A ratio tells us how badly we're throttled, independent of units.

Answer: 3.94 GB/s, only 12.5% of intended.

Verify: Sanity by factors: width fell $16 \to 4$ = $\frac{1}{4}$ ; per-lane fell $1.969 \to 0.985$ = $\frac{1}{2}$ . Product $\frac{1}{4} \times \frac{1}{2} = \frac{1}{8} = 12.5%$ ✓ — matches the direct ratio.

Worked example Example 5 — Cell E: the full-duplex ×2 trap

Statement. A spec sheet screams "PCIe 5.0 x16 = 128 GB/s!" Your one-way calc gave ~63 GB/s. Who's right?

Forecast: is the sheet lying, or counting something you're not?

One-way: $16 \times 3.938 = 63.02$ GB/s. Why this step? This is payload in one direction (e.g. host→GPU).
Aggregate: each lane is full-duplex, so TX and RX happen at once: $63.02 \times 2 = 126.03$ GB/s. Why this step? Bidirectional aggregate adds both directions — the ×2 the marketing uses.

Answer: Both are "right" but answer different questions: 63 GB/s one-way, ~126 GB/s aggregate (rounded to "128" in ads).

Verify: The marketing "128" comes from rounding raw $32 GT/s \times 16 \times 2/8 = 128$ GB/s ignoring encoding. With encoding it's 126.03 — so the honest aggregate is $126.03$ , and the raw-bits-ignored figure is $128$ . Both traceable ✓.

Worked example Example 6 — Cell F: zero and degenerate inputs

Statement. Three edge cases: (a) a disconnected card negotiates x0; (b) the smallest real link, Gen 1.0 x1; (c) what happens to the formula as $N \to 0$ .

Forecast: does the formula break at zero, or gracefully give zero?

(a) $N = 0$ : $0 \times (anything) = 0$ GB/s. Why this step? Multiplication by zero — no lanes means no channels means no data. The formula stays valid at the degenerate point.
(b) Gen 1.0 x1: $1 \times 0.250 = 0.250$ GB/s. Why this step? Smallest generation, smallest width — the floor of the whole table.
(c) Limit: since bandwidth $= N \times (const)$ , it is linear in $N$ , so as $N \to 0$ it smoothly approaches 0 with slope = per-lane rate. Why this step? Linearity means no surprises, no discontinuity — the "highway with zero lanes" carries zero traffic exactly.

Answer: x0 → 0 GB/s; Gen 1.0 x1 → 0.250 GB/s; the map is continuous and passes through the origin.

Verify: Plug $N = 1$ into Gen 1.0: $2.5 \times 0.8/8 = 0.25$ ✓. Plug $N = 0$ : exactly $0$ ✓. Slope between them = $0.25$ GB/s per lane, matching the per-lane rate ✓.

Here is that linearity drawn — bandwidth is a straight ray from the origin, one line per generation:

Figure — PCIe lanes, links, and bandwidth

Worked example Example 7 — Cell G: run the chain backwards

Statement. A device sustains 7.0 GB/s one-way on a PCIe 4.0 link. What is the minimum lane width it must have negotiated?

Forecast: x2, x4, or x8?

Per-lane Gen 4.0 rate = 1.969 GB/s. Why this step? To find lanes we invert $BW = N \times (per-lane)$ , so we need the per-lane value.
Solve for $N$ : $N = \frac{7.0}{1.969} = 3.55$ . Why this step? Dividing observed BW by per-lane rate gives the fractional lanes needed.
Round up to a legal width: $3.55 \to$ next valid is x4. Why this step? Lanes come only in 1, 2, 4, 8, 16. You cannot buy 3.55 lanes; x2 (=3.94 GB/s cap... wait, $2 \times 1.969 = 3.94 < 7.0$ ) is too small, so x4 is the minimum that fits.

Answer: x4 (which caps at $4 \times 1.969 = 7.877$ GB/s, comfortably above 7.0).

Verify: Check x2 fails: $2 \times 1.969 = 3.94 < 7.0$ ✗. Check x4 works: $7.877 \geq 7.0$ ✓. So x4 is indeed the minimum.

Worked example Example 8 — Cell H: real-world bottleneck

Statement. An NVMe SSD is rated 7000 MB/s and runs on PCIe 4.0 x4, but you route it through a chipset uplink shared with other devices, leaving it effectively PCIe 3.0 x4. Can it still hit 7000 MB/s? What's the ceiling?

Forecast: does the drive keep its rating, or does the uplink strangle it?

Drive rating in GB/s: $7000/1000 = 7.0$ GB/s. Why this step? Match units to the link (GB/s) before comparing — the Cell B lesson.
Effective link ceiling: Gen 3.0 x4 = $4 \times 0.985 = 3.94$ GB/s. Why this step? The slowest link in the path sets the ceiling — that's the bottleneck rule.
Compare: $7.0 > 3.94$ , so the link, not the drive, is the limit. Why this step? Bandwidth of a chain = its narrowest link, exactly like water through the thinnest pipe.

Answer: No — capped at 3.94 GB/s, roughly 56% of the drive's rating ( $3.94/7.0$ ).

Verify: On the correct Gen 4.0 x4 link the ceiling is $4 \times 1.969 = 7.877 \geq 7.0$ ✓ (drive would fit), confirming the loss is purely the generation downgrade. Ratio $3.94/7.877 = 0.5$ ✓ — Gen 3 is exactly half Gen 4 per lane.

Worked example Example 9 — Cell I: the exam twist

Statement. Exam question: "A PCIe 2.0 x16 link and a PCIe 3.0 x8 link — which delivers more one-way bandwidth?" The trap: more lanes ≠ more bandwidth.

Forecast: the x16 (more lanes) or the x8 (newer gen)?

PCIe 2.0 x16: per-lane $= 5.0 \times 0.8/8 = 0.5$ GB/s, so $16 \times 0.5 = 8.0$ GB/s. Why this step? Old gen has cheap $η = 0.8$ and low $R$ , but lots of lanes.
PCIe 3.0 x8: per-lane $= 0.985$ GB/s, so $8 \times 0.985 = 7.877$ GB/s. Why this step? Newer gen, richer $η$ , but half the lanes.
Compare: $8.0 > 7.877$ . Why this step? The direct numbers settle it; intuition ("newer is faster") would mislead you here.

Answer: The PCIe 2.0 x16 wins, barely — 8.0 vs 7.88 GB/s.

Verify: Difference $8.0 - 7.877 = 0.123$ GB/s ≈ 1.6% — a photo-finish that punishes anyone who guessed by gut ✓.

Recall Quick self-test

Gen 3.0 x8 one-way bandwidth? ::: ≈ 7.88 GB/s A card reads "x16 @ x8" — how many real lanes? ::: 8 (the second number is negotiated width) Why do bandwidth contributions multiply, not add? ::: $R$ , $η$ , and $N$ are independent proportional factors; adding would mix incompatible units An x16 slot bifurcated x8/x8 — bandwidth per device? ::: half the x16 link each; total conserved Marketing "128 GB/s" for Gen5 x16 vs your 63 GB/s — the gap? ::: they quote bidirectional aggregate (×2) and often ignore encoding

Where to go next

The encoding fractions came from 8b10b Encoding and 128b130b Encoding.
Why lanes physically exist as pairs: PCIe Electrical Signaling.
How the CPU/chipset decides which slot gets how many lanes: Motherboard Lane Allocation and PCIe Bifurcation.
Whether a card actually needs the full width: GPU Bandwidth Requirements.
The big picture: PCIe Architecture Overview and the parent PCIe lanes, links, and bandwidth.