6.3.3 · D5Interconnects, Buses & SoC
Question bank — PCIe lanes, links, and bandwidth
This page is a thinking gym, not a calculator. Every item below targets a place where PCIe intuition quietly breaks — a hidden assumption, a boundary you never tested. Answer each one out loud in a sentence before you reveal. If you can only say "yes" or "no", you haven't understood it yet.
New here? Build the machinery first on PCIe lanes, links, and bandwidth, then come back and try to break your own understanding.
The vocabulary you must own before the traps
Every question below leans on four ideas. If any of these is fuzzy, the traps will feel like magic instead of reasoning. Build them here first — with pictures — so nothing later is a stranger.
True or false — justify
A "true/false" is a lie if you can't say why. Give the reason first.
A PCIe lane can only send data in one direction at a time.
False. A lane is full-duplex — it has a separate TX pair and RX pair (see the definition above), so it transmits and receives simultaneously. The "take turns" model belongs to old shared parallel buses, not PCIe.
An x16 physical slot always delivers x16 electrical lanes.
False. The slot is just a connector with 16 lane positions; how many are actually wired and negotiated depends on the CPU/chipset. A slot can be "x16 physical, x4 electrical" — read it as x16 @ x4.
Doubling the number of lanes doubles the bandwidth.
True. Lanes are independent parallel channels, so bandwidth scales linearly with lane count: lanes carry times one lane's data rate. No shared clock bottleneck between them.
Doubling the raw signaling rate (GT/s = wire bits per second) always doubles the usable data rate.
Mostly true, but watch the encoding. Within one encoding scheme it doubles. Across the Gen 2→3 boundary the encoding also changed (8b/10b → 128b/130b), so the payload fraction jumped from 0.8 to 0.9846 — Gen 3's usable rate more than doubled per GT/s even though 8→8 GT/s isn't 2× of 5 GT/s.
PCIe 3.0 is exactly twice as fast as PCIe 2.0.
Roughly, but not exactly. Gen 2 gives Gbps/lane; Gen 3 gives Gbps/lane. That's ~1.97×, not a clean 2× — the encoding-efficiency jump is doing extra work on top of the raw-rate change.
The "32 GB/s" a vendor prints for PCIe 3.0 x16 is the bandwidth you get in one direction.
False. That figure is the bidirectional aggregate (TX + RX summed). One-directional is ~15.75 GB/s. For a GPU streaming textures from RAM, one direction is what actually matters.
1 Gbps in PCIe math equals bits per second.
False. PCIe uses decimal units: 1 Gbps bits/s, and 1 GB/s bytes/s. This is why the byte conversion is a clean ÷8 with no messy binary factor.
128b/130b is more complex circuitry but less efficient than 8b/10b.
False on efficiency. 128b/130b keeps ~98.46% of the wire for payload () vs 8b/10b's 80% (). It is more complex, but that's the price paid for recovering the wasted 20%.
Bifurcation reduces the total bandwidth available at a slot.
False. PCIe Bifurcation splits an x16 into (say) two x8 links; the sum still equals the original x16. What drops is the per-device cap, not the aggregate.
Spot the error
Each statement below contains one wrong reasoning step. Name it.
"My SSD is PCIe 4.0 x4, so it will always read at 7.88 GB/s."
The error is treating the link ceiling as the achieved throughput. 7.88 GB/s is the theoretical PCIe max; real speed is capped lower by NVMe protocol overhead, NAND read latency, and the controller. See NVMe Protocol.
"PCIe 3.0 wastes 20% to encoding just like Gen 1 and 2."
Wrong generation for the number. Gen 3 switched to 128b/130b (2 header bits per 130), wasting only ~1.5%, not 20%. The 20% figure is the of 8b/10b and belongs to Gen 1 and 2 only.
"I moved my GPU to the second x16 slot, so it still runs at x16."
The physical slot being x16 doesn't guarantee x16 electrical lanes. Second slots are commonly wired x4 from the chipset (often an older gen too), so the link negotiates far lower.
"To get GB/s I multiply Gbps by 8."
Backwards. There are 8 bits in a byte, so you divide Gbps by 8 to get GB/s. Multiplying would inflate the answer 64×.
"Full-duplex means the link runs twice as fast."
It doesn't speed up either direction; it means both directions run at full rate at the same time. Each direction's data rate is unchanged — you just get two of them concurrently.
"GT/s already tells me the payload bits per second."
No — GigaTransfers/s counts every wire bit, including the encoding bits. You must multiply by encoding efficiency (0.8 or 0.9846) before it becomes payload throughput (Gbps).
"An NVMe drive plugged into a PCIe 3.0 slot loses its data — it's incompatible with Gen 4."
PCIe is backward and forward compatible; the link just negotiates the lowest common generation. A Gen 4 drive in a Gen 3 slot runs fine at Gen 3 speeds, no data loss.
Why questions
The "why" is where the understanding lives. Each answer walks the chain, not just the verdict.
Why does PCIe use differential pairs (two inverted wires) instead of one wire per signal?
Chain: (1) external noise couples into both wires nearly equally; (2) the receiver computes wire-A minus wire-B; (3) that subtraction cancels the shared (common-mode) noise while the real signal, which is opposite on the two wires, adds. Result: a clean signal survives even at multi-GHz toggling — see PCIe Electrical Signaling.
Why did the standard tolerate 20% encoding waste for Gens 1 and 2 but not later?
Chain: (1) 8b/10b spends 2 of every 10 bits keeping the signal DC-balanced; (2) at 2.5–5 GT/s the lost 20% is a small absolute number and the balancing logic is cheap; (3) as raw rate climbed, 20% of a huge number became too much bandwidth to throw away, so the standard moved the balancing job into a scrambler and switched to 128b/130b, cutting waste to ~1.5%.
Why do we multiply raw rate by encoding efficiency rather than subtract a fixed number?
The overhead is a fraction of every transfer, not a fixed lump — every 130 wire bits carries exactly 128 payload bits regardless of speed. A fraction scales with the rate, so multiplication (), not subtraction, models it.
Why does the vendor advertise the bidirectional (aggregate) figure?
Because it's the bigger number and technically real (the link genuinely moves that much total across both directions). Just know it double-counts, so halve it when reasoning about one-way work like a GPU read.
Why can two x8 devices in a bifurcated x16 each be slower than a single x16 device would be?
Chain: (1) PCIe Bifurcation physically splits the 16 lanes into two groups of 8; (2) each device is negotiated over only its 8 lanes; (3) bandwidth is linear in lanes, so each caps at half the x16 ceiling. The aggregate is preserved, but no single device can borrow the other's lanes.
Why does encoding efficiency for 128b/130b (≈0.9846) never quite reach 1.0?
Those 2 header bits per 130 are a mandatory sync header marking where each 128-bit block starts; without them the receiver can't find frame boundaries and the stream is unreadable. So is the unavoidable cost of framing — see 128b130b Encoding.
Edge cases
The boundaries reveal whether a rule is actually understood — including messy real-world electrical ones.
What bandwidth does a PCIe link with zero negotiated lanes provide?
Effectively a dead link — 0 lanes means 0 GB/s. In practice the device fails to enumerate; the OS won't see it at all, which is the classic "not detected" symptom of a bad seat or dead slot.
If a Gen 5 device is placed in a Gen 1 slot, which generation wins?
The lowest common generation — Gen 1. The link trains down to what both endpoints support, so a Gen 5 SSD in a Gen 1 slot crawls at Gen 1 rates.
A drive advertises "x4" but the slot only wires 1 electrical lane. What happens?
The link negotiates down to the narrowest common width — x1. It still works, at a quarter of the intended bandwidth, reported as "x4 @ x1".
Why does adding more lanes eventually force the controller to deskew them, and what breaks if it can't?
Lanes are separate physical wires of slightly different length, so the same word arrives at slightly different times — lane skew. The receiver buffers each lane and re-aligns them before reassembling the word; if skew exceeds the buffer, the word can't be rebuilt and the link retrains to a narrower or slower mode to cope.
Why can't we just push GT/s arbitrarily high on the same trace?
At higher frequencies the signal loses energy in the copper and neighboring pairs leak into each other (crosstalk). Past a limit the eye the receiver samples closes and bit errors spike — which is exactly why Gen 4/5 demand shorter traces, retimers, and stricter PCIe Electrical Signaling.
A GPU is under heavy load and thermally throttles; monitoring shows the link dropped from x16 to x8 mid-session. Why?
Heat and marginal signal integrity can raise the error rate until the link retrains to a more robust (narrower/slower) state to stay reliable — a link retraining event. It's the controller trading bandwidth for correctness, not a broken slot.
At exactly the point where measured throughput equals the theoretical link max, what should you suspect?
You almost never reach it, so hitting or exceeding it means a measurement or unit error (e.g. mixing GB/s decimal vs binary, or counting bidirectional as unidirectional). Real data always sits below the ceiling.
A single lane at Gen 5 (≈3.94 GB/s) vs four lanes at Gen 3 (≈3.94 GB/s) — same bandwidth, so are they interchangeable?
Same aggregate number, but not interchangeable. The Gen 5 x1 needs one clean ultra-high-speed lane and stricter signaling; the Gen 3 x4 needs four lanes routed and negotiated. Compatibility, Motherboard Lane Allocation, and signal integrity differ even when the GB/s matches.
For a GPU that mostly reads from system RAM, does the RX or TX direction dominate, and does full-duplex help?
Reads flow host→device (RX at the GPU), so that direction dominates while TX sits mostly idle. Full-duplex doesn't add speed to the busy direction — so a GPU is bounded by one direction's bandwidth, not the aggregate. See GPU Bandwidth Requirements.
Recall Quick self-test before you leave
Cover the answers and reason each in one sentence. Does an x16 slot guarantee x16 bandwidth? ::: No — physical width ≠ negotiated electrical width; always check "x16 @ x?". Where does the ×0.8 in Gen 2 come from? ::: 8b/10b: 8 payload bits per 10 wire bits, so efficiency = 8/10 = 0.8. Is the vendor's headline GB/s one-way or aggregate? ::: Aggregate (bidirectional) — halve it for one-directional work. When two encodings differ, why not just subtract overhead? ::: Overhead is a fraction of every transfer, so it scales — multiply by efficiency.