PCIe lanes, links, and bandwidth: Question bank — Hinglish deep dive

6.3.3 · D5 · Hardware › Interconnects, Buses & SoC › PCIe lanes, links, and bandwidth

Yeh page ek thinking gym hai, calculator nahi. Neeche har item ek aisi jagah ko target karta hai jahan PCIe intuition quietly break hoti hai — ek hidden assumption, ek boundary jo tumne kabhi test nahi ki. Har ek ko reveal karne se pehle ek sentence mein zor se answer do. Agar tum sirf "haan" ya "nahi" bol sako, tab samajh lo ki samajh abhi bani nahi hai.

Naye ho? Pehle PCIe lanes, links, and bandwidth par machinery build karo, phir wapas aao aur apni understanding ko tod ke dekho.

Woh vocabulary jo tumhare paas traps se pehle honi chahiye

Neeche har question char ideas pe lean karta hai. Agar inme se koi bhi fuzzy hai, toh traps magic jaisi lagenge reasoning ki jagah. Inhe pehle yahan build karo — pictures ke saath — taaki baad mein kuch bhi stranger na lage.

Figure — PCIe lanes, links, and bandwidth

Definition Differential pair — "TX pair" aur "RX pair" ka matlab

Ek differential pair hai do wires jo same signal carry karti hain lekin inverted hoke (jab ek high jaati hai, doosri low jaati hai). Receiver sirf unke beech ka difference padhta hai. Ek TX pair woh do wires hain jis par device transmit karta hai; ek RX pair woh do wires hain jis par woh receive karta hai. "Electrical lanes" ka matlab hai ki yeh pairs actually physically wired hain aur toggling kar rahi hain — as opposed to ek slot jiske paas connector holes toh hain lekin kuch ke peeche koi wire nahi hai. Figure ka middle panel dekho: do squiggles jo ek doosre ka mirror karti hain, aur unka clean difference.

Do wires per direction kyun? Kisi nearby cable se noise dono wires ko almost equally hit karti hai. Unhe subtract karne se woh common-mode noise cancel ho jaati hai, aur yahi woh cheez hai jo wire ko billions of times per second toggle karne deti hai bina garble hue. Iske baare mein aur jaankari PCIe Electrical Signaling mein milegi.

Definition 0.8 aur 0.9846 kahan se aate hain — encoding efficiency

Encoding efficiency simply hai payload bits ÷ wire bits.

8b/10b encoding (Gen 1–2): har 8 data bits ko 10 wire bits mein re-code kiya jaata hai. 2 extra bits signal ko DC-balanced rakhte hain (barabar 1s aur 0s taaki receiver ka clock locked rahe) aur frequent transitions guarantee karte hain. Efficiency $= \frac{8}{10} = 0.8$ — yahan se "×0.8" aata hai, koi magic number nahi. Dekho 8b10b Encoding.
128b/130b encoding (Gen 3+): har 128 data bits ke aage 2-bit sync header prepend hota hai, jisse 130 wire bits bante hain. Woh 2 bits receiver ko batate hain "yahan ek block shuru hota hai" taaki woh frame boundaries find kar sake. Efficiency $= \frac{128}{130} \approx 0.9846$ . Dekho 128b130b Encoding.

8b/10b ko full 20% kyun chahiye lekin 128b/130b ko sirf ~1.5%: 8b/10b apne extra bits continuously spend karta hai (har group of 8 ko balance karte hue), jabki 128b/130b sirf 130-bit block mein ek baar 2 bits spend karta hai kyunki balancing ka kaam alag tarike se (scrambling se) handle hota hai — toh bahut kam bits "waste" hoti hain. Figure ka right panel dono bars ko side by side dikhata hai.

True ya false — justify karo

Ek "true/false" ek jhooth hai agar tum why nahi bol sakte. Pehle reason do.

Ek PCIe lane ek baar mein sirf ek hi direction mein data bhej sakti hai.

False. Ek lane full-duplex hoti hai — iske paas alag TX pair aur RX pair hoti hai (upar definition dekho), toh yeh simultaneously transmit aur receive karti hai. "Baari baari" wala model purani shared parallel buses ka hai, PCIe ka nahi.

Ek x16 physical slot hamesha x16 electrical lanes deliver karta hai.

False. Slot sirf ek connector hai jisme 16 lane positions hain; actually kitni wired hain aur negotiate hui hain yeh CPU/chipset par depend karta hai. Ek slot "x16 physical, x4 electrical" ho sakta hai — ise x16 @ x4 padho.

Lanes ki sankhya double karne se bandwidth double ho jaati hai.

True. Lanes independent parallel channels hain, toh bandwidth lane count ke saath linearly scale karti hai:

N

lanes

N

guna ek lane ka data rate carry karte hain. Unke beech koi shared clock bottleneck nahi hota.

Raw signaling rate (GT/s = wire bits per second) double karne se usable data rate hamesha double ho jaati hai.

Zyada tar sach, lekin encoding dhyaan se dekho. Ek hi encoding scheme ke andar yeh double hoti hai. Gen 2→3 boundary ke paar encoding bhi badli (8b/10b → 128b/130b), toh payload fraction 0.8 se 0.9846 tak jump kar gaya — Gen 3 ka usable rate per GT/s se bhi zyada double ho gaya, bhaale hi 8→8 GT/s, 5 GT/s ka 2× nahi hai.

PCIe 3.0 exactly PCIe 2.0 se do guna fast hai.

Roughly, lekin exactly nahi. Gen 2 deta hai

5.0 \times 0.8 = 4.0

Gbps/lane; Gen 3 deta hai

8.0 \times \frac{128}{130} \approx 7.88

Gbps/lane. Yeh ~1.97× hai, clean 2× nahi — encoding-efficiency jump raw-rate change ke upar extra kaam kar raha hai.

Vendor jo "32 GB/s" PCIe 3.0 x16 ke liye print karta hai woh ek direction mein milne wali bandwidth hai.

False. Yeh figure bidirectional aggregate hai (TX + RX summed). Ek-directional ~15.75 GB/s hai. Ek GPU ke liye jo RAM se textures stream kar raha hai, actually ek direction hi matter karta hai.

PCIe math mein 1 Gbps

2^{30}

bits per second ke barabar hai.

False. PCIe decimal units use karta hai: 1 Gbps

= 1 0^{9}

bits/s, aur 1 GB/s

= 1 0^{9}

bytes/s. Isliye byte conversion clean ÷8 hai, koi messy binary factor nahi.

128b/130b zyada complex circuitry hai lekin 8b/10b se kam efficient hai.

Efficiency par False. 128b/130b wire ka ~98.46% payload ke liye rakhta hai (

\frac{128}{130}

) vs 8b/10b ka 80% (

\frac{8}{10}

). Yeh zyada complex zaroor hai, lekin yeh woh price hai jo waste hue 20% ko recover karne ke liye pay kiya jaata hai.

Bifurcation ek slot par available total bandwidth ko reduce karta hai.

False. PCIe Bifurcation ek x16 ko (maan lo) do x8 links mein split karta hai; sum abhi bhi original x16 ke barabar rehta hai. Jo drop hota hai woh hai per-device cap, aggregate nahi.

Error dhundho

Neeche har statement mein ek galat reasoning step hai. Use name karo.

"Mera SSD PCIe 4.0 x4 hai, toh yeh hamesha 7.88 GB/s par read karega."

Error yeh hai ki link ceiling ko achieved throughput maana ja raha hai. 7.88 GB/s theoretical PCIe max hai; real speed NVMe protocol overhead, NAND read latency, aur controller se neeche cap hoti hai. Dekho NVMe Protocol.

"PCIe 3.0 Gen 1 aur 2 ki tarah encoding mein 20% waste karta hai."

Number ke liye galat generation. Gen 3 ne 128b/130b pe switch kiya (130 mein 2 header bits), sirf ~1.5% waste karte hue, 20% nahi. 20% figure

1 - \frac{8}{10}

wali 8b/10b ki hai aur sirf Gen 1 aur 2 ke liye hai.

"Maine apna GPU doosre x16 slot mein move kiya, toh yeh abhi bhi x16 par run karta hai."

Physical slot ka x16 hona electrical lanes ka x16 hona guarantee nahi karta. Doosre slots commonly x4 chipset se wired hote hain (often older gen bhi), toh link bahut lower negotiate karta hai.

"GB/s pane ke liye main Gbps ko 8 se multiply karta hoon."

Ulta hai. Ek byte mein 8 bits hote hain, toh GB/s pane ke liye Gbps ko 8 se divide karo. Multiply karne se answer 64× inflate ho jaata.

"Full-duplex ka matlab hai link do guna fast run karta hai."

Yeh kisi bhi direction ko speed up nahi karta; iska matlab hai dono directions full rate par ek saath run karti hain. Har direction ki data rate unchanged rehti hai — tum bas unhe concurrently paate ho, do baar nahi.

"GT/s pehle se hi mujhe payload bits per second bata deta hai."

Nahi — GigaTransfers/s har wire bit count karta hai, including encoding bits. Yeh payload throughput (Gbps) banne se pehle tumhe encoding efficiency (0.8 ya 0.9846) se multiply karna hoga.

"Gen 3 slot mein lagaya gaya NVMe drive apna data kho deta hai — yeh Gen 4 ke saath incompatible hai."

PCIe backward aur forward compatible hai; link sirf lowest common generation negotiate karta hai. Ek Gen 4 drive Gen 3 slot mein theek se Gen 3 speeds par run karta hai, koi data loss nahi.

Why questions

"Why" mein hi understanding rehti hai. Har answer chain walk karta hai, sirf verdict nahi.

PCIe ek signal per wire ki jagah differential pairs (do inverted wires) kyun use karta hai?

Chain: (1) external noise dono wires mein almost equally couple hoti hai; (2) receiver wire-A minus wire-B compute karta hai; (3) woh subtraction shared (common-mode) noise cancel kar deta hai jabki real signal, jo dono wires par opposite hai, add hota hai. Result: multi-GHz toggling par bhi ek clean signal survive karta hai — dekho PCIe Electrical Signaling.

Standard ne Gens 1 aur 2 ke liye 20% encoding waste tolerate kiya lekin baad mein nahi, kyun?

Chain: (1) 8b/10b har 10 bits mein se 2 bits signal DC-balanced rakhne mein spend karta hai; (2) 2.5–5 GT/s par lost 20% ek chhota absolute number hai aur balancing logic sasta hai; (3) jaise raw rate badhti gayi, ek bade number ka 20% bahut zyada bandwidth throw away karna ban gaya, toh standard ne balancing ka kaam ek scrambler mein shift kiya aur 128b/130b par switch kiya, waste ~1.5% tak cut karte hue.

Hum raw rate se encoding efficiency kyun multiply karte hain, na ki ek fixed number subtract karte hain?

Overhead har transfer ka ek fraction hai, ek fixed lump nahi — har 130 wire bits exactly 128 payload bits carry karte hain speed se regardless. Ek fraction rate ke saath scale karta hai, isliye multiplication (

\times \frac{128}{130}

), subtraction nahi, isko model karta hai.

Vendor bidirectional (aggregate) figure kyun advertise karta hai?

Kyunki yeh bada number hai aur technically real hai (link genuinely utna total dono directions mein move karta hai). Bas yeh jaano ki yeh double-count karta hai, isliye ek-way kaam jaise GPU read ke baare mein reasoning karte waqt ise half kar lo.

Ek bifurcated x16 mein do x8 devices ek single x16 device se slower kyun ho sakte hain?

Chain: (1) PCIe Bifurcation physically 16 lanes ko do groups of 8 mein split karta hai; (2) har device sirf apne 8 lanes par negotiate hota hai; (3) bandwidth lanes mein linear hai, toh har device x16 ceiling ke half par cap ho jaata hai. Aggregate preserve hota hai, lekin koi bhi single device doosre ki lanes borrow nahi kar sakta.

128b/130b ke liye encoding efficiency (≈0.9846) kabhi 1.0 tak kyun nahi pahunchti?

Woh 130 mein 2 header bits ek mandatory sync header hain jo mark karte hain ki har 128-bit block kahan shuru hota hai; inke bina receiver frame boundaries nahi dhundh sakta aur stream unreadable hogi. Toh

\frac{128}{130} < 1

framing ki unavoidable cost hai — dekho 128b130b Encoding.

Edge cases

Boundaries yeh reveal karti hain ki koi rule actually samjha gaya hai ya nahi — real-world electrical ones bhi.

Zero negotiated lanes wala PCIe link kitni bandwidth provide karta hai?

Effectively ek dead link — 0 lanes matlab 0 GB/s. Practice mein device enumerate karne mein fail ho jaata hai; OS ise bilkul nahi dekhega, jo ek bad seat ya dead slot ka classic "not detected" symptom hai.

Agar ek Gen 5 device Gen 1 slot mein rakha jaye, toh kaun si generation jeetti hai?

Lowest common generation — Gen 1. Link train down karta hai wahan tak jo dono endpoints support karte hain, toh Gen 1 slot mein ek Gen 5 SSD Gen 1 rates par crawl karega.

Ek drive "x4" advertise karta hai lekin slot sirf 1 electrical lane wire karta hai. Kya hoga?

Link negotiate down karta hai narrowest common width par — x1. Yeh phir bhi kaam karta hai, intended bandwidth ke ek-quarter par, "x4 @ x1" report hota hai.

Zyada lanes add karne se eventually controller ko unhe deskew karna kyun padta hai, aur agar nahi kar saka toh kya break hota hai?

Lanes alag-alag physical wires hain jo thodi alag length ki hoti hain, toh ek hi word thoda alag time par pahunchta hai — lane skew. Receiver har lane ko buffer karta hai aur word reassemble karne se pehle unhe re-align karta hai; agar skew buffer se zyada ho, toh word rebuild nahi ho sakta aur link cope karne ke liye narrower ya slower mode mein retrain karta hai.

Hum same trace par GT/s ko arbitrarily high kyun nahi push kar sakte?

Higher frequencies par signal copper mein energy lose karta hai aur neighboring pairs ek doosre mein leak karte hain (crosstalk). Ek limit ke baad eye jo receiver sample karta hai woh close ho jaata hai aur bit errors spike ho jaate hain — exactly isliye Gen 4/5 shorter traces, retimers, aur stricter PCIe Electrical Signaling demand karte hain.

Ek GPU heavy load par hai aur thermally throttle karta hai; monitoring dikhata hai ki link mid-session x16 se x8 par drop ho gaya. Kyun?

Heat aur marginal signal integrity error rate itna badha sakti hai jab tak link retrain nahi kar leta ek zyada robust (narrower/slower) state mein reliable rehne ke liye — yeh ek link retraining event hai. Controller bandwidth ko correctness ke liye trade kar raha hai, koi broken slot nahi.

Exactly us point par jahan measured throughput theoretical link max ke barabar ho, tumhe kya suspect karna chahiye?

Tum almost kabhi ise reach nahi karte, toh ise hit karna ya exceed karna matlab hai koi measurement ya unit error hai (jaise GB/s decimal vs binary mix karna, ya bidirectional ko unidirectional count karna). Real data hamesha ceiling ke neeche hoti hai.

Ek single lane at Gen 5 (≈3.94 GB/s) vs four lanes at Gen 3 (≈3.94 GB/s) — same bandwidth, toh kya yeh interchangeable hain?

Same aggregate number, lekin interchangeable nahi. Gen 5 x1 ko ek clean ultra-high-speed lane aur stricter signaling chahiye; Gen 3 x4 ko chaar lanes route aur negotiate karne chahiye. Compatibility, Motherboard Lane Allocation, aur signal integrity differ karte hain bhaale GB/s match kare.

Ek GPU ke liye jo mostly system RAM se read karta hai, kya RX ya TX direction dominate karta hai, aur kya full-duplex help karta hai?

Reads host→device flow karti hain (GPU par RX), toh woh direction dominate karti hai jabki TX mostly idle rehta hai. Full-duplex busy direction mein speed add nahi karta — toh ek GPU ek direction ki bandwidth se bound hai, aggregate se nahi. Dekho GPU Bandwidth Requirements.

Recall Jaane se pehle quick self-test

Answers cover karo aur har ek ko ek sentence mein reason karo. Kya ek x16 slot x16 bandwidth guarantee karta hai? ::: Nahi — physical width ≠ negotiated electrical width; hamesha check karo "x16 @ x?". Gen 2 mein ×0.8 kahan se aata hai? ::: 8b/10b: 10 wire bits mein 8 payload bits, toh efficiency = 8/10 = 0.8. Vendor ka headline GB/s one-way hai ya aggregate? ::: Aggregate (bidirectional) — one-directional kaam ke liye ise half karo. Jab do encodings differ karti hain, overhead subtract kyun nahi karte? ::: Overhead har transfer ka fraction hai, toh yeh scale karta hai — efficiency se multiply karo.