PCIe lanes, links, and bandwidth: Visual walkthrough

This is the visual walkthrough. We start from a single wiggling wire and end at "PCIe 4.0 x16 gives 31.5 GB/s one way." Every step has a picture. If you meet a symbol you have not seen, it gets built here — nothing is assumed from the parent note.

Step 1 — What a lane physically is

WHAT. A lane is not one wire. It is two wire-pairs: one pair carries data out of the device (the TX pair, Transmit), one pair carries data in (the RX pair, Receive). Each pair is two copper traces carrying mirror-image voltages — this is differential signaling and it kills electrical noise, because noise hits both wires equally and cancels when you subtract them.

WHY start here. Everything downstream — the "×2 for both directions" at the very end — only makes sense once you see that a lane already has two separate roads baked in.

PICTURE. Look at the figure: the black lines are the four physical wires of ONE lane. The red arrows show the two independent directions of traffic. They never wait for each other — that is what full-duplex means.

Figure — PCIe lanes, links, and bandwidth

Related depth: PCIe Electrical Signaling.

Step 2 — What one wire actually sends: the raw transfer rate

WHAT. On ONE pair, the voltage flips up and down. Each flip that the receiver can resolve is one transfer — one raw symbol on the wire. The speed of these flips is the raw transfer rate, measured in GT/s (GigaTransfers per second = $1 0^{9}$ transfers each second).

R_{raw} = 8.0 GT/s (PCIe 3.0, per lane, per direction)

Term by term:

$R_{raw}$ — the symbol we invent for "raw flips per second on the wire."
$8.0$ — the number the standard fixes for Gen 3.
$GT/s$ — the unit; transfers, not yet bits of your data, because some of those transfers are overhead (Step 3).

WHY "GT/s" and not "Gbps" yet. We must NOT call these gigabits of payload — some transfers carry housekeeping. Naming the raw quantity separately keeps us honest. A transfer here happens to equal one raw bit, but the payload count is smaller.

PICTURE. The red trace is the voltage on one pair. Each shaded slot is one transfer. Count the slots per second → that is $R_{raw}$ .

Gen	$R_{raw}$ per lane
1.0	2.5 GT/s
2.0	5.0 GT/s
3.0	8.0 GT/s
4.0	16.0 GT/s
5.0	32.0 GT/s

Step 3 — The tax: encoding overhead

WHAT. The receiver needs to know where one bit ends and the next begins (clock recovery) and needs the signal to have no long runs of all-1s or all-0s (DC balance). To guarantee this, PCIe never sends your raw data alone — it wraps it. This wrapping is encoding overhead.

PCIe 1.0 & 2.0 use 8b/10b: every 8 data bits are shipped as 10 wire bits. Efficiency $= \frac{8}{10} = 0.8$ → you keep 80%.
PCIe 3.0+ use 128b/130b: every 128 data bits are shipped as 130 wire bits. Efficiency $= \frac{128}{130} \approx 0.9846$ → you keep ~98.46%.

Define the encoding efficiency:

E = \frac{data bits}{wire bits}

numerator = the bits you actually wanted to send.
denominator = the bits the wire actually carried (data + wrapper).
The ratio is always $< 1$ : overhead can only take away, never add.

WHY change the scheme at Gen 3? 8b/10b throws away 20% forever — brutal at high speed. 128b/130b throws away only ~1.5%, at the cost of harder circuitry. At Gen-3 speeds that trade finally paid off.

PICTURE. Two bars of equal wire length. In the red-tipped tiny slice you see the wasted bits: a fat 20% chunk for 8b/10b, a sliver of 1.5% for 128b/130b. The black portion is your real data.

More: 8b10b Encoding · 128b130b Encoding.

Step 4 — Payload bits per second on one lane, one direction

WHAT. Multiply what the wire moves ( $R_{raw}$ ) by the fraction that is real data ( $E$ ):

R_{data} = R_{raw} \times E

For PCIe 3.0:

R_{data} = 8.0 GT/s \times \frac{128}{130} = 7.877 Gbps

Term by term:

$R_{raw} = 8.0$ — transfers/s on the wire (Step 2).
$E = \frac{128}{130}$ — fraction that is payload (Step 3).
$R_{data} = 7.877$ — payload gigabits per second. NOW we may say "Gbps," because the overhead has been removed.

WHY multiply and not subtract? Overhead is a proportion of the stream, not a fixed lump. A proportion scales with the rate → multiply by the ratio.

PICTURE. A funnel: 8.0 GT/s pours in the top, the red neck (the ×128/130 squeeze) narrows it, and 7.877 Gbps of pure data drips out.

Step 5 — Bits to bytes

WHAT. People buy drives in gigaBYTES per second, and 1 byte = 8 bits, so divide:

B_{1} = \frac{R _{data}}{8}

For PCIe 3.0:

B_{1} = \frac{7.877 Gbps}{8} = 0.985 GB/s per lane

$R_{data} = 7.877$ — payload bits/s (Step 4).
$8$ — bits in a byte (pure unit conversion, no physics).
$B_{1} = 0.985$ — GB/s carried by one lane in one direction.

WHY divide by exactly 8, not 8.2 or 10? The encoding tax was already paid in Step 4. Here it is only the definition "8 bits make a byte." Nothing physical, just relabelling.

PICTURE. Eight small black bit-boxes snap together into one red byte-box, with the arithmetic $\div 8$ over the arrow.

Step 6 — Add the lanes (the parallel-highway step)

WHAT. A link of width $N$ is $N$ lanes side by side, all pushing data at once and independently. So bandwidth scales linearly:

B_{link} = N \times B_{1}

For PCIe 3.0 x16:

B_{link} = 16 \times 0.985 = 15.75 GB/s (one direction)

$N = 16$ — lane count (the "x16").
$B_{1} = 0.985$ — one lane's GB/s (Step 5).
$B_{link} = 15.75$ — GB/s for the whole link, one way.

WHY linear and not more? Lanes do not cooperate or share a clock's payload — each is a separate road. Two roads carry exactly twice one road. No synergy, no penalty.

PICTURE. Sixteen identical red arrows stacked as parallel lanes; the total-width brace on the right reads $N \times B_{1}$ .

Common widths (why a slot may not use all its pins): Motherboard Lane Allocation · PCIe Bifurcation.

Step 6b — Re-run the chain in Gen 4: reaching the headline number

WHAT. Everything above used Gen 3's $R_{raw} = 8.0$ GT/s. The only thing that changes for Gen 4 is that number — it doubles to $16.0$ GT/s. Same encoding $E = \frac{128}{130}$ , same $\div 8$ , same $\times N$ . Run the identical pipeline:

B_{1}^{Gen4} = \frac{16.0 \times \frac{128}{130}}{8} = 1.969 GB/s per lane

B_{link}^{Gen4, x16} = 16 \times 1.969 = 31.5 GB/s (one direction)

Term by term:

$16.0$ — Gen-4 raw rate, exactly double Gen 3.
$\frac{128}{130}$ — unchanged encoding efficiency.
$\div 8$ — unchanged bits-to-bytes.
$\times 16$ — the x16 lane count.
$31.5$ — this is our promised headline: PCIe 4.0 x16, one-way.

WHY show this separately. The intro promised "PCIe 4.0 x16 → 31.5 GB/s one-way," so here is the explicit standalone calculation. Notice Gen 4 = exactly $2 \times$ every Gen-3 number, because doubling only $R_{raw}$ doubles the whole product.

PICTURE. The Gen-3 result (15.75) and the Gen-4 result (31.5) side by side; the red arrow marks the ×2 that comes purely from doubling $R_{raw}$ .

Step 7 — Both directions at once (aggregate vs one-way)

WHAT. Recall Step 1: each lane has a TX road AND an RX road running together. So there are two honest numbers (using our Gen-4 x16 headline):

B_{oneway} = 31.5 GB/s, B_{agg} = 2 \times 31.5 = 63.0 GB/s

$B_{oneway}$ — what you get reading or writing (e.g. a GPU pulling textures from RAM).
$B_{agg}$ — TX + RX added together; the big marketing number.

WHY keep them separate? Most workloads are lopsided — a GPU mostly reads. Quoting the aggregate 63 GB/s when you can only use 31.5 GB/s one-way is the single most common way people over-estimate PCIe.

PICTURE. The red TX arrow and a black RX arrow, each labelled 31.5 GB/s, meeting a "+" that yields 63.0 GB/s aggregate.

Step 8 — Edge and degenerate cases

Every scenario the reader can hit:

N = 1 (x1 link). Gen 4: $B_{link} = 1 \times 1.969 = 1.969$ GB/s. The formula still holds — one lane is just the base case.
Gen 1 / Gen 2 (8b/10b). $E$ jumps to $0.8$ . PCIe 2.0 x1 $= 5.0 \times 0.8/8 = 0.5$ GB/s. The only thing that changes across generations is $R_{raw}$ and $E$ ; Steps 4–7 are untouched.
Slot wider than lanes wired ("x16 @ x8"). The physical connector has 16 pins but only 8 are electrically live. Use $N = 8$ , the negotiated width, never the slot's shape. See Motherboard Lane Allocation.
Bifurcation (x16 → x8/x8). The 16 lanes split into two independent $N = 8$ links. Each device sees $8 \times 1.969 = 15.752$ GB/s (Gen 4, rounds to 15.75); the two together sum back to the full $31.5$ GB/s. You divided, you did not lose. See PCIe Bifurcation.
Zero active lanes ( $N = 0$ ). Link is down — $B = 0$ . Not a trick; the linear formula degrades gracefully to "no lanes, no data."

PICTURE. A 16-pin slot outline with only 8 pins glowing red ("x16 @ x8"), beside a bifurcated slot split down the middle into two red x8 halves.

The one-picture summary

Every layer, one flow, in Gen 4: raw transfers → subtract encoding tax → bits to bytes → multiply by lanes → double for both directions, ending at the headline 31.5 GB/s one-way.

Recall Feynman retelling — say it back in plain words

A lane is four wires: two carry data out, two carry data in, and they work at the same time. On one of those roads the voltage flips a fixed number of times per second — call that the raw rate, in GigaTransfers. But not every flip is your data: some flips are wrappers so the receiver can find the beat and stay balanced. Old PCIe wasted 1 in 5; new PCIe wastes only ~15 in 1000. Multiply the raw rate by "fraction that's real data" and you get real bits per second. Divide by 8 because a byte is 8 bits, and now you have GB/s for one lane, one way. Stack $N$ lanes side by side and just multiply by $N$ — they're separate roads, so it's plain addition. For Gen 4 the raw rate is doubled to 16 GT/s, so every number doubles: one lane is 1.969 GB/s, and x16 is 31.5 GB/s one way. Finally, since every lane already had an out-road and an in-road, you can double again if you count both directions (63 GB/s aggregate) — but for a GPU pulling data one way, the single-direction 31.5 GB/s is the honest number. Corner cases: fewer live pins than the slot shows? use the real lane count. Split a x16 into two x8? each half is smaller, but nothing vanished.