PCIe lanes, links, and bandwidth: Visual walkthrough

6.3.3 · D2 · Hardware › Interconnects, Buses & SoC › PCIe lanes, links, and bandwidth

Yeh ek visual walkthrough hai. Hum ek akele wiggling wire se shuru karte hain aur "PCIe 4.0 x16 gives 31.5 GB/s one way" tak pahunchte hain. Har step mein ek picture hai. Agar tumhe koi symbol naya lage, toh woh yahan build kiya jayega — parent note se kuch assume nahi kiya gaya hai.

Step 1 — Lane physically kya hota hai

KYA HAI. Ek lane ek wire nahi hoti. Yeh do wire-pairs hoti hain: ek pair data device se bahar le jaati hai (TX pair, Transmit), ek pair data andar laati hai (RX pair, Receive). Har pair mein do copper traces hote hain jo mirror-image voltages carry karte hain — yeh differential signaling hai aur yeh electrical noise ko khatam kar deta hai, kyunki noise dono wires ko equally hit karti hai aur subtract karne par cancel ho jaati hai.

YAHAN SE KYUN shuru karein. Aage ki har cheez — bilkul end mein "×2 for both directions" — tabhi samajh aati hai jab tum dekho ki ek lane mein pehle se hi do alag roads bani hui hain.

PICTURE. Figure mein dekho: black lines EK lane ki chaar physical wires hain. Red arrows traffic ki do independent directions dikhate hain. Woh kabhi ek doosre ka wait nahi karte — iska matlab full-duplex hai.

Figure — PCIe lanes, links, and bandwidth

Related depth: PCIe Electrical Signaling.

Step 2 — Ek wire actually kya bhejti hai: raw transfer rate

KYA HAI. EK pair par, voltage upar neeche flip karta hai. Har ek flip jo receiver resolve kar sake woh ek transfer hai — wire par ek raw symbol. Inhi flips ki speed raw transfer rate hai, jo GT/s mein measure hoti hai (GigaTransfers per second = $1 0^{9}$ transfers har second).

R_{raw} = 8.0 GT/s (PCIe 3.0, per lane, per direction)

Term by term:

$R_{raw}$ — woh symbol jo humne "wire par raw flips per second" ke liye banaya.
$8.0$ — woh number jo standard ne Gen 3 ke liye fix kiya.
$GT/s$ — unit; transfers, abhi tak tumhare data ke bits nahi, kyunki kuch transfers overhead hote hain (Step 3).

"GT/s" kyun, "Gbps" nahi abhi. Hum inhe gigabits of payload nahi keh sakte — kuch transfers housekeeping carry karte hain. Raw quantity ko alag naam dena humein honest rakhta hai. Yahan ek transfer ek raw bit ke barabar hota hai, lekin payload count chhota hota hai.

PICTURE. Red trace ek pair par voltage hai. Har shaded slot ek transfer hai. Slots per second gino → wahi $R_{raw}$ hai.

Gen	$R_{raw}$ per lane
1.0	2.5 GT/s
2.0	5.0 GT/s
3.0	8.0 GT/s
4.0	16.0 GT/s
5.0	32.0 GT/s

Step 3 — Tax: encoding overhead

KYA HAI. Receiver ko jaanna chahiye ki ek bit kahan khatam hoti hai aur agla kahan shuru hota hai (clock recovery), aur signal mein lambe runs of all-1s ya all-0s nahi hone chahiye (DC balance). Yeh guarantee karne ke liye, PCIe kabhi tumhara raw data akela nahi bhejta — woh usse wrap karta hai. Yeh wrapping encoding overhead hai.

PCIe 1.0 & 2.0 8b/10b use karte hain: har 8 data bits ko 10 wire bits ke roop mein bheja jaata hai. Efficiency $= \frac{8}{10} = 0.8$ → tumhare paas 80% bachta hai.
PCIe 3.0+ 128b/130b use karte hain: har 128 data bits ko 130 wire bits ke roop mein bheja jaata hai. Efficiency $= \frac{128}{130} \approx 0.9846$ → tumhare paas ~98.46% bachta hai.

Encoding efficiency define karo:

E = \frac{data bits}{wire bits}

numerator = woh bits jo tum actually bhejna chahte the.
denominator = woh bits jo wire actually carry karti hai (data + wrapper).
Ratio hamesha $< 1$ hota hai: overhead sirf le sakta hai, kuch add nahi kar sakta.

Gen 3 par scheme kyun badli? 8b/10b hamesha ke liye 20% throw away karta hai — high speed par brutal. 128b/130b sirf ~1.5% throw away karta hai, lekin harder circuitry ki cost par. Gen-3 speeds par woh trade finally pay off hua.

PICTURE. Do bars of equal wire length. Red-tipped tiny slice mein tum waste bits dekhte ho: 8b/10b ke liye ek mota 20% chunk, 128b/130b ke liye 1.5% ka ek sliver. Black portion tumhara real data hai.

More: 8b10b Encoding · 128b130b Encoding.

Step 4 — Ek lane, ek direction mein payload bits per second

KYA HAI. Wire kya move karti hai ( $R_{raw}$ ) usse real data ka fraction ( $E$ ) se multiply karo:

R_{data} = R_{raw} \times E

PCIe 3.0 ke liye:

R_{data} = 8.0 GT/s \times \frac{128}{130} = 7.877 Gbps

Term by term:

$R_{raw} = 8.0$ — wire par transfers/s (Step 2).
$E = \frac{128}{130}$ — woh fraction jo payload hai (Step 3).
$R_{data} = 7.877$ — payload gigabits per second. AB hum "Gbps" keh sakte hain, kyunki overhead hata diya gaya hai.

Subtract kyun nahi, multiply kyun? Overhead stream ka ek proportion hai, fixed lump nahi. Ek proportion rate ke saath scale karta hai → ratio se multiply karo.

PICTURE. Ek funnel: 8.0 GT/s upar se daala jaata hai, red neck (×128/130 squeeze) usse narrow karta hai, aur 7.877 Gbps pure data neeche tapakta hai.

Step 5 — Bits se bytes

KYA HAI. Log drives gigaBYTES per second mein khareedते hain, aur 1 byte = 8 bits, toh divide karo:

B_{1} = \frac{R _{data}}{8}

PCIe 3.0 ke liye:

B_{1} = \frac{7.877 Gbps}{8} = 0.985 GB/s per lane

$R_{data} = 7.877$ — payload bits/s (Step 4).
$8$ — ek byte mein bits (pure unit conversion, koi physics nahi).
$B_{1} = 0.985$ — ek lane mein ek direction mein GB/s.

Exactly 8 se kyun divide karo, 8.2 ya 10 se nahi? Encoding tax Step 4 mein already pay ho chuki hai. Yahan sirf definition hai "8 bits ek byte banate hain." Kuch physical nahi, sirf relabelling.

PICTURE. Aath chhote black bit-boxes ek red byte-box mein snap hote hain, arrow ke upar arithmetic $\div 8$ likha hai.

Step 6 — Lanes add karo (parallel-highway step)

KYA HAI. Width $N$ ka ek link $N$ lanes side by side hain, jo sab ek saath aur independently data push karte hain. Toh bandwidth linearly scale karta hai:

B_{link} = N \times B_{1}

PCIe 3.0 x16 ke liye:

B_{link} = 16 \times 0.985 = 15.75 GB/s (one direction)

$N = 16$ — lane count ("x16").
$B_{1} = 0.985$ — ek lane ka GB/s (Step 5).
$B_{link} = 15.75$ — puri link ke liye GB/s, ek direction mein.

Linear kyun, zyada kyun nahi? Lanes cooperate nahi karte ya clock ka payload share nahi karte — har ek ek alag road hai. Do roads exactly ek road se double carry karti hain. Koi synergy nahi, koi penalty nahi.

PICTURE. Solah identical red arrows parallel lanes ke roop mein stacked; dayi taraf total-width brace $N \times B_{1}$ likhta hai.

Common widths (ek slot apne saare pins kyun use nahi karta): Motherboard Lane Allocation · PCIe Bifurcation.

Step 6b — Gen 4 mein chain dobara chalao: headline number tak pahuncho

KYA HAI. Upar sab kuch Gen 3 ka $R_{raw} = 8.0$ GT/s use karta tha. Gen 4 ke liye sirf wahi number badalta hai — yeh double hokar $16.0$ GT/s ho jaata hai. Same encoding $E = \frac{128}{130}$ , same $\div 8$ , same $\times N$ . Identical pipeline chalao:

B_{1}^{Gen4} = \frac{16.0 \times \frac{128}{130}}{8} = 1.969 GB/s per lane

B_{link}^{Gen4, x16} = 16 \times 1.969 = 31.5 GB/s (one direction)

Term by term:

$16.0$ — Gen-4 raw rate, Gen 3 se exactly double.
$\frac{128}{130}$ — unchanged encoding efficiency.
$\div 8$ — unchanged bits-to-bytes.
$\times 16$ — x16 lane count.
$31.5$ — yeh hamara promised headline hai: PCIe 4.0 x16, one-way.

Yeh alag kyun dikhao. Intro ne "PCIe 4.0 x16 → 31.5 GB/s one-way" promise kiya tha, toh yahan explicit standalone calculation hai. Notice karo Gen 4 = exactly $2 \times$ har Gen-3 number, kyunki sirf $R_{raw}$ double karne se pura product double ho jaata hai.

PICTURE. Gen-3 result (15.75) aur Gen-4 result (31.5) side by side; red arrow woh ×2 mark karta hai jo purely $R_{raw}$ double karne se aata hai.

Step 7 — Dono directions ek saath (aggregate vs one-way)

KYA HAI. Step 1 yaad karo: har lane mein ek TX road AUR ek RX road saath chalti hain. Toh do honest numbers hain (humara Gen-4 x16 headline use karke):

B_{oneway} = 31.5 GB/s, B_{agg} = 2 \times 31.5 = 63.0 GB/s

$B_{oneway}$ — jo tum padhte ya likhte waqt milta hai (e.g. ek GPU textures RAM se pull karta hai).
$B_{agg}$ — TX + RX ek saath add; bada marketing number.

Inhe alag kyun rakho? Zyatatar workloads lopsided hote hain — ek GPU mostly reads karta hai. 63 GB/s aggregate quote karna jab tum one-way sirf 31.5 GB/s use kar sakte ho, woh sabse common tarika hai jisse log PCIe over-estimate karte hain.

PICTURE. Red TX arrow aur ek black RX arrow, dono 31.5 GB/s label kiye hue, ek "+" se milte hain jo 63.0 GB/s aggregate yield karta hai.

Step 8 — Edge aur degenerate cases

Har woh scenario jo reader face kar sakta hai:

N = 1 (x1 link). Gen 4: $B_{link} = 1 \times 1.969 = 1.969$ GB/s. Formula abhi bhi kaam karta hai — ek lane sirf base case hai.
Gen 1 / Gen 2 (8b/10b). $E$ $0.8$ ho jaata hai. PCIe 2.0 x1 $= 5.0 \times 0.8/8 = 0.5$ GB/s. Generations ke across sirf $R_{raw}$ aur $E$ badalta hai; Steps 4–7 untouched rehte hain.
Slot zyada wide hai lanes wired se ("x16 @ x8"). Physical connector mein 16 pins hain lekin sirf 8 electrically live hain. $N = 8$ , negotiated width use karo, slot ki shape kabhi nahi. Dekho Motherboard Lane Allocation.
Bifurcation (x16 → x8/x8). 16 lanes do independent $N = 8$ links mein split ho jaati hain. Har device $8 \times 1.969 = 15.752$ GB/s dekhta hai (Gen 4, rounds to 15.75); dono milake poore $31.5$ GB/s pe waapis aate hain. Tumne divide kiya, kuch khoya nahi. Dekho PCIe Bifurcation.
Zero active lanes ( $N = 0$ ). Link down hai — $B = 0$ . Koi trick nahi; linear formula gracefully "no lanes, no data" tak degrade hota hai.

PICTURE. Ek 16-pin slot outline jisme sirf 8 pins red glow kar rahe hain ("x16 @ x8"), ek bifurcated slot ke saath jo beeche se do red x8 halves mein split hai.

Ek-picture summary

Har layer, ek flow, Gen 4 mein: raw transfers → encoding tax ghatao → bits to bytes → lanes se multiply karo → dono directions ke liye double karo, aur end mein headline 31.5 GB/s one-way milti hai.

Recall Feynman retelling — plain words mein wapas bol ke dikhao

Ek lane chaar wires hai: do data bahar carry karte hain, do andar, aur woh ek saath kaam karte hain. Un roads mein se ek par voltage ek fixed number of times per second flip karta hai — usse raw rate kaho, GigaTransfers mein. Lekin har flip tumhara data nahi hota: kuch flips wrappers hote hain taaki receiver beat pakad sake aur balanced rahe. Purana PCIe 5 mein se 1 waste karta tha; naya PCIe sirf ~15 per 1000 waste karta hai. Raw rate ko "real data wala fraction" se multiply karo aur tumhe real bits per second milte hain. 8 se divide karo kyunki ek byte 8 bits hota hai, aur ab tumhare paas ek lane, ek way ke liye GB/s hai. $N$ lanes side by side stack karo aur bas $N$ se multiply karo — woh separate roads hain, toh yeh plain addition hai. Gen 4 ke liye raw rate 16 GT/s par double ho jaati hai, toh har number double ho jaata hai: ek lane 1.969 GB/s hai, aur x16 ek direction mein 31.5 GB/s hai. Finally, kyunki har lane mein pehle se hi ek out-road aur ek in-road thi, tum dobara double kar sakte ho agar dono directions count karo (63 GB/s aggregate) — lekin ek GPU ke liye jo ek taraf se data pull karta hai, single-direction 31.5 GB/s honest number hai. Corner cases: slot jitne pins dikhata hai usse kam live pins hain? Real lane count use karo. Ek x16 ko do x8 mein split karo? Har half chhota hai, lekin kuch vanish nahi hua.