6.3.3 · D1Interconnects, Buses & SoC

Foundations — PCIe lanes, links, and bandwidth

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Before you can trust a bandwidth number, you must earn every symbol behind it. Below we build them from absolute zero — each one gets a plain meaning, a picture, and a reason the topic needs it. The parent note (PCIe lanes, links, and bandwidth) assumes all of these; here we make none of them assumed.


1. A bit, and "bits per second"

Picture a single wire whose voltage jumps up and down over time. Each moment it "means" a 1 or a 0.

Figure — PCIe lanes, links, and bandwidth

Look at the amber trace in the figure: every time the line is up it's a 1, every time it's down it's a 0. If those up/down changes happen fast, we push more bits per second.

Why the topic needs it: Everything called "bandwidth" is ultimately a count of bits per second. If you don't own "bit per second," every later number is a mystery.


2. Differential signalling — why TWO wires carry one bit

Figure — PCIe lanes, links, and bandwidth

In the figure, the top cyan wire and the bottom cyan wire are mirror images. Any electrical noise (grey wiggle) hits both wires equally, so when the receiver subtracts one from the other, the noise cancels and the clean signal survives.

Why the topic needs it: The parent note says "one lane = TX pair + RX pair." A pair means two wires. Without this idea, "pair" is just a word. This is the hardware reason PCIe is noise-tolerant at multi-GHz speeds. See PCIe Electrical Signaling for the deeper electrical story.


3. Lane = TX pair + RX pair (full-duplex)

A lane stacks two differential pairs:

  • TX pair — carries data out of a device.
  • RX pair — carries data in to a device.
Figure — PCIe lanes, links, and bandwidth

The figure shows one lane = 4 physical wires total: a TX pair (amber, arrow pointing right) and an RX pair (cyan, arrow pointing left). Both arrows fire simultaneously — that's full-duplex.

Why the topic needs it: The lane is the atom of everything. Bandwidth is "per-lane rate × number of lanes," so if the lane is fuzzy, the whole formula is fuzzy.


Why the topic needs it: Step 5 of the parent's derivation multiplies a single-lane rate by . That is the link width. Also crucial: the physical slot (the plastic connector) can be wider than the electrical link actually wired to it — see Motherboard Lane Allocation and PCIe Bifurcation.


5. The "transfer" and GT/s

Why this tool and not Gbps here? Because payload depends on the encoding scheme, which differs between generations. GT/s pins down the physical wire speed cleanly; we then multiply by an efficiency to get real payload. Mixing them up is the #1 source of "why is my drive slow?" confusion.


6. Encoding overhead and efficiency (the fraction)

Two schemes appear in the topic:

Why the topic needs it: GT/s counts all wire bits; efficiency is the fraction that is real data. Without it you'd overstate Gen 1/2 bandwidth by 25%. Deeper mechanics live in 8b10b Encoding and 128b130b Encoding.


7. Bytes, and dividing by 8

Why the topic needs it: SSD makers quote MB/s and GB/s; PCIe math starts in Gbps. The ÷ 8 bridges the two worlds — see NVMe Protocol and GPU Bandwidth Requirements.


8. Putting the symbols together (preview of the master formula)

Now that every symbol is earned, the parent's whole derivation is one line:


Prerequisite map

bit and bits per second

differential pair two wires

lane TX pair plus RX pair

link and width N

raw rate GT per s

encoding efficiency E

byte and divide by 8

PCIe bandwidth formula

Read it bottom-up: the four foundations (link width , raw rate , efficiency , byte conversion) all feed the single bandwidth formula at the top.


Equipment checklist

Self-test: cover the right side and answer each before revealing.

What is a bit, physically?
A single wire held HIGH (1) or LOW (0) — the smallest unit of information.
How many wires make one differential pair, and why?
Two, carrying inverted copies; the receiver reads their difference so shared noise cancels.
How many physical wires are in one PCIe lane?
Four — a TX pair (2 wires) and an RX pair (2 wires).
What does "full-duplex" mean for a lane?
It sends and receives simultaneously on separate wires — no taking turns.
What does the "x" in x16 mean and what symbol do we call it?
It's a multiplication sign for lane count; we call the count , so x16 means .
Why is the wire speed given in GT/s instead of Gbps?
GT/s counts raw wire transfers before removing encoding overhead; Gbps is payload only.
What is the efficiency of 8b/10b and of 128b/130b?
and .
Why do we add extra bits in encoding at all?
To recover the clock from the data and keep voltage balanced, since there is no separate clock wire.
How do you convert Gbps to GB/s and why?
Divide by 8, because 8 bits make 1 byte.
Can a physical x16 slot be electrically x4?
Yes — the connector shape is independent of how many lanes are actually wired.