Foundations — PCIe lanes, links, and bandwidth

6.3.3 · D1 · Hardware › Interconnects, Buses & SoC › PCIe lanes, links, and bandwidth

Kisi bhi bandwidth number par trust karne se pehle, uske peeche har ek symbol ko earn karna padega. Neeche hum unhe bilkul zero se build karte hain — har ek ko ek plain meaning milti hai, ek picture milti hai, aur ek reason milta hai ki topic ko wo kyun chahiye. Parent note (PCIe lanes, links, and bandwidth) in sab ko assume karta hai; yahan hum inhe assumed nahi rehne dete.

1. Ek bit, aur "bits per second"

Ek single wire ki picture lo jiska voltage time ke saath upar-neeche jaata rehta hai. Har moment wo ya to 1 "mean" karta hai ya 0.

Figure mein amber trace dekho: jab bhi line upar hai wo 1 hai, jab bhi neeche hai wo 0 hai. Agar ye upar-neeche changes fast hote hain, to hum zyada bits per second push karte hain.

Topic ko ye kyun chahiye: Jo bhi "bandwidth" kehlata hai wo ultimately bits per second ka count hai. Agar "bit per second" clear nahi hai, to baad ke har number ek mystery hai.

2. Differential signalling — kyun DO wires ek bit carry karti hain

Figure mein, upar wali cyan wire aur neeche wali cyan wire mirror images hain. Koi bhi electrical noise (grey wiggle) dono wires ko equally hit karta hai, isliye jab receiver ek ko doosre se subtract karta hai, noise cancel ho jaata hai aur clean signal bach jaata hai.

Topic ko ye kyun chahiye: Parent note kehta hai "one lane = TX pair + RX pair." Ek pair ka matlab hai do wires. Is idea ke bina, "pair" bas ek word hai. Ye hardware ka reason hai ki PCIe multi-GHz speeds par noise-tolerant kyun hai. Deeper electrical story ke liye PCIe Electrical Signaling dekho.

3. Lane = TX pair + RX pair (full-duplex)

Ek lane do differential pairs ko stack karta hai:

• TX pair — data ko device se bahar le jaata hai.
• RX pair — data ko device mein andar laata hai.

Figure mein ek lane = kul 4 physical wires dikhta hai: ek TX pair (amber, arrow right ki taraf point kar raha hai) aur ek RX pair (cyan, arrow left ki taraf point kar raha hai). Dono arrows ek saath fire hote hain — yahi full-duplex hai.

Topic ko ye kyun chahiye: Lane har cheez ka atom hai. Bandwidth hai "per-lane rate × number of lanes," isliye agar lane fuzzy hai, to pura formula fuzzy hai.

4. Link aur link width ($N$, "xN" notation)

Topic ko ye kyun chahiye: Parent ke derivation ke step 5 mein single-lane rate ko $N$ se multiply kiya jaata hai. Wo $N$ hi link width hai. Ye bhi crucial hai: physical slot (plastic connector) electrically link se wider ho sakta hai jo actually wire kiya gaya ho — Motherboard Lane Allocation aur PCIe Bifurcation dekho.

5. "Transfer" aur GT/s

Ye tool kyun, Gbps nahi? Kyunki payload encoding scheme par depend karta hai, jo generations ke beech alag hoti hai. GT/s physical wire speed ko cleanly pin down karta hai; phir hum real payload paane ke liye efficiency se multiply karte hain. Inhe mix karna "meri drive slow kyun hai?" confusion ka #1 source hai.

6. Encoding overhead aur efficiency (fraction)

Topic mein do schemes aate hain:

Topic ko ye kyun chahiye: GT/s saare wire bits count karta hai; efficiency wo fraction hai jo real data hai. Iske bina aap Gen 1/2 bandwidth ko 25% overstate kar dete. Deeper mechanics 8b10b Encoding aur 128b130b Encoding mein hain.

7. Bytes, aur 8 se divide karna

Topic ko ye kyun chahiye: SSD makers MB/s aur GB/s mein quote karte hain; PCIe math Gbps se start hoti hai. ÷ 8 dono worlds ko bridge karta hai — NVMe Protocol aur GPU Bandwidth Requirements dekho.

8. Symbols ko saath jodna (master formula ka preview)

Ab jab har symbol earn ho chuka hai, parent ka pura derivation ek hi line hai:

Prerequisite map

Ise bottom-up padhо: char foundations (link width $N$, raw rate $R$, efficiency $E$, byte conversion) saare upar wale single bandwidth formula ko feed karte hain.

Equipment checklist

Self-test: right side cover karo aur reveal karne se pehle har ek ka jawab do.