Exercises — PCIe lanes, links, and bandwidth

WHAT we do: identify the generation, then look up its encoding. Gen 1.0 and 2.0 both use 8b/10b. For every 8 payload bits, 10 bits go on the wire. Efficiency $=\frac{8}{10}=0.8=80\%$. The extra 2 bits per 10 are spent on DC balance and clock recovery — real bits on the wire, but not your data.

Raw rate: PCIe 4.0 runs at $16.0$ GT/s per lane (double Gen 3's $8.0$ GT/s). Encoding: Gen 3 and up use 128b/130b, efficiency $\approx 0.9846$. GT/s means GigaTransfers per second — bit-toggles on the wire, before removing encoding overhead. It is not yet "gigabits of your data."

Step A — raw rate: Gen 3 $=8.0$ GT/s. Step B — apply efficiency (WHY: GT/s counts every symbol on the wire, including overhead; multiplying by the efficiency strips the encoding overhead and leaves only payload bits). The result is measured in Gbps — gigabits per second, i.e. billions of payload bits per second: $8.0\times \frac{128}{130}=7.877\text{Gbps}$ Step C — convert bits to bytes (WHY: engineers want GB/s, and there are 8 bits in a byte, so divide by 8): $\frac{7.877}{8}=0.985\text{GB/s}$ Answer: $\approx 0.985$ GB/s per lane, one direction.

Step A — raw rate: Gen 4 $=16.0$ GT/s. Step B — apply efficiency (WHY: remove the 128b/130b encoding overhead so we keep only payload bits). Result is in Gbps, gigabits of payload per second: $16.0\times \frac{128}{130}=15.754\text{Gbps}$ Step C — convert bits to bytes (WHY: 8 bits per byte, so divide by 8 to get GB/s): $\frac{15.754}{8}=1.969\text{GB/s per lane}$ Step D — scale by lanes (WHY: 8 independent parallel channels each carry this rate simultaneously): $8\times 1.969=15.75\text{GB/s}$ Answer: $\approx 15.75$ GB/s one direction.

Step A — raw rate: Gen 2 $=5.0$ GT/s, encoding 8b/10b so efficiency $0.8$. Step B — apply efficiency (WHY: strip the 20% 8b/10b overhead to leave payload bits, giving Gbps): $5.0\times 0.8=4.0\text{Gbps}$ Step C — convert bits to bytes (WHY: 8 bits per byte, so divide by 8 to reach GB/s): $\frac{4.0}{8}=0.5\text{GB/s per lane}$ Step D — scale by lanes (WHY: 16 parallel channels): $16\times 0.5=8.0$ GB/s. Answer: $8.0$ GB/s one direction.

Step A — theoretical max, PCIe 4.0 x4: $4\times 1.969=7.876\text{GB/s}$ Step B — put both numbers in the same units (WHY: MB/s vs GB/s): $7000\text{MB/s}=7.0\text{GB/s}$ Step C — compare: $7.0<7.876$ ✓ — physically possible. Step D — utilization: $\frac{7.0}{7.876}\times 100\approx 88.9\%$ The remaining ~11% is lost to NVMe command overhead, NAND read latency, and controller limits.

Intended — Gen 4 x16: $16\times 1.969=31.51$ GB/s. Actual — Gen 3 x4: two downgrades at once (generation and width): $4\times 0.985=3.94\text{GB/s}$ Loss (GB/s): $31.51-3.94=27.57$ GB/s. Retained fraction: $\frac{3.94}{31.51}\times 100\approx 12.5\%$ — you kept only one-eighth. Reason it's so brutal: width fell by $4\times$ (x16→x4) and per-lane rate fell by ~$2\times$ (Gen4→Gen3). Multiply the two: $4\times 2=8\times$ slower. See GPU Bandwidth Requirements.

Gen 3 x16: $16\times 0.985=15.75$ GB/s. Gen 4 x8: $8\times 1.969=15.75$ GB/s. They are equal (both $\approx 15.75$ GB/s). WHY: Gen 4 doubles the per-lane rate versus Gen 3, so halving the lane count exactly cancels it out. This is the general "one generation up = half the lanes for the same throughput" rule.

(a) Each device sees x8: $8\times 1.969=15.75$ GB/s. (b) Combined: $15.75\times 2=31.5$ GB/s — identical to the original x16 total. (c) Nothing is destroyed — the 16 lanes were divided, not lost. But each individual device is now capped at 15.75 GB/s instead of the full 31.5 GB/s. Bifurcation splits, it does not shrink.

Per lane, Gen 5 (32.0 GT/s): $\frac{32.0\times \frac{128}{130}}{8}=\frac{31.508}{8}=3.938\text{GB/s}$ One direction, x16: $16\times 3.938=63.02$ GB/s. Bidirectional aggregate (WHY: each lane is full-duplex — TX and RX run simultaneously): $63.02\text{TX}+63.02\text{RX}=126.03\text{GB/s}$ Why quote one-direction for texture reads: the GPU is pulling data one way (RAM → GPU) during a texture fetch. Only the RX direction is doing that work. The aggregate double-counts a return path you aren't using, so it overstates real throughput. See PCIe Electrical Signaling for why the two directions are physically separate wire pairs.

Per-lane rates we will use:

• Gen 5 lane $=3.938$ GB/s (from L4·Q2).
• Gen 4 lane $=1.969$ GB/s (from L2·Q2).

Step 1 — how many CPU lanes does the GPU need? Requirement $\ge 32$ GB/s. $\frac{32}{3.938}=8.13\text{lanes}$ PCIe widths are quantized to powers of two, so 8.13 rounds up to the next valid width — x16. Check: Gen 5 x8 gives $8\times 3.938=31.5$ GB/s, which is below 32, so x8 fails the strict target. The GPU must take the full x16. GPU delivered: $16\times 3.938=63.02$ GB/s (comfortably $\ge 32$). This consumes all 16 CPU lanes.

Step 2 — where does the SSD go? The 16 CPU lanes are now fully committed to the GPU, so the SSD cannot use them. Route it to the 4 chipset lanes (PCIe 4.0) instead: $4\times 1.969=7.88\text{GB/s}$ SSD delivered: $7.88$ GB/s $\ge 7$ GB/s ✓.

Concrete plan:

• GPU → CPU lanes, Gen 5 x16 → 63.02 GB/s (meets $\ge 32$).
• SSD → chipset lanes, Gen 4 x4 → 7.88 GB/s (meets $\ge 7$).

Mastery insight: the 16 Gen-5 CPU lanes give at most 31.5 GB/s to an x8 device, so a strict "$\ge 32$ to the GPU" forces the GPU to claim the whole x16. That leaves zero CPU lanes for the SSD, which is exactly why the second device must live on chipset lanes (Motherboard Lane Allocation). The arithmetic — not the slot layout — dictates the routing.

Verify Gen 5 x16 one-direction: $16\times \frac{32.0\times \frac{128}{130}}{8}=16\times 3.938=63.02\text{GB/s}✓$ Gen 4 x16 one-direction: $16\times 1.969=31.51$ GB/s. Gen 3 x16 one-direction: $16\times 0.985=15.75$ GB/s. Gen 3 x16 aggregate (both directions): $15.75\times 2=31.5$ GB/s. Comparison: $31.5\approx 31.51$ — the Gen 3 x16 aggregate numerically equals the Gen 4 x16 one-direction. But it is NOT a real match: aggregate counts TX+RX; the Gen 4 one-direction figure is achievable in a single stream. A one-way texture pull cannot borrow the return path. So the equality is a coincidence of arithmetic, not of usable throughput. Mastery insight: always compare like conventions — one-direction vs one-direction, aggregate vs aggregate. Mixing them produces "equal" numbers that describe totally different capabilities.

One-line self-checks — answer before revealing. What are the two encoding efficiencies and their generations? ::: 8b/10b = 0.8 for Gen 1–2; 128b/130b ≈ 0.9846 for Gen 3+. In the master chain, when exactly do you divide by 8? ::: Once, after applying efficiency, to convert bits to bytes — before scaling by lane count. Why does Gen 4 x8 tie Gen 3 x16? ::: Gen 4 doubles per-lane rate; halving lanes cancels it → same 15.75 GB/s. Does bifurcation reduce total bandwidth? ::: No — it divides the lanes; total is unchanged, but each device is capped at its share. Which figure to quote for a one-way GPU texture read? ::: One-direction bandwidth, never the bidirectional aggregate.