PCIe lanes, links, and bandwidth: Exercises — Hinglish deep dive

6.3.3 · D4 · Hardware › Interconnects, Buses & SoC › PCIe lanes, links, and bandwidth

Yeh page ek self-test ladder hai. Har problem parent note pe build karti hai. Pehle har ek ko paper pe solve karo, phir collapsible solution kholो. Difficulty paanch levels mein badhti hai — koi level skip mat karo.

Shuru karne se pehle, yeh ek core chain apne dimag mein rakho (hum ise parent note mein derive kar chuke hain):

Neeche diya reference card kaise padhein. Bars har generation ki x16 one-direction bandwidth GB/s mein dikhate hain (har bar ke upar floating number). Har bar ke andar, cream text mein, us generation ki per-lane rate hai — upar wala number 16 se divide karo aur woh mil jaata hai. Card ko sanity check ki tarah use karo: problem finish karne ke baad, us generation ka bar dhundho aur confirm karo ki tumhara per-lane figure cream number se match karta hai, aur tumhara x16 total bar ke upar wale number se match karta hai. Chhoti annotation notice karo jo dikhati hai kahan encoding Gen 2 aur Gen 3 ke beech 8b/10b se 128b/130b mein switch hoti hai — isliye bars us boundary pe clean $2 \times$ se thoda zyada jump karte hain.

Figure — PCIe lanes, links, and bandwidth

Level 1 — Recognition

Goal: sahi row se sahi number bina galti ke padhna.

L1·Q1

Ek device PCIe 2.0 x1 link negotiate karta hai. Woh kaun si encoding use karta hai, aur uski efficiency fraction aur percentage mein kya hai?

Recall Solution

HUM KYA KARTE HAIN: generation identify karo, phir uski encoding lookup karo. Gen 1.0 aur 2.0 dono 8b/10b use karte hain. Har 8 payload bits ke liye, 10 bits wire pe jaate hain. Efficiency $= \frac{8}{10} = 0.8 = 80%$ . Extra 2 bits per 10, DC balance aur clock recovery pe kharche jaate hain — wire pe real bits hain, lekin tumhara data nahi.

L1·Q2

Ek device PCIe 4.0 x1 negotiate karta hai. Uski raw signaling rate (GT/s mein) aur encoding scheme batao.

Recall Solution

Raw rate: PCIe 4.0, $16.0$ GT/s per lane pe chalta hai (Gen 3 ke $8.0$ GT/s ka double). Encoding: Gen 3 aur upar 128b/130b use karte hain, efficiency $\approx 0.9846$ . GT/s matlab GigaTransfers per second — wire pe bit-toggles, encoding overhead hatane se pehle. Yeh abhi "gigabits of your data" nahi hai.

Level 2 — Application

Goal: ek single value ke liye master chain ko end-to-end run karna.

L2·Q1

Ek single PCIe 3.0 x1 lane ki one-direction data rate GB/s mein compute karo. Har step dikhao.

Recall Solution

Step A — raw rate: Gen 3 $= 8.0$ GT/s. Step B — efficiency apply karo (KYUN: GT/s wire pe har symbol count karta hai, overhead bhi; efficiency se multiply karne par encoding overhead strip ho jaata hai aur sirf payload bits bachte hain). Result Gbps mein measure hota hai — gigabits per second, yaani billions of payload bits per second: $8.0 \times \frac{128}{130} = 7.877 Gbps$ Step C — bits ko bytes mein convert karo (KYUN: engineers GB/s chahte hain, aur ek byte mein 8 bits hote hain, isliye 8 se divide karo): $\frac{7.877}{8} = 0.985 GB/s$ Answer: $\approx 0.985$ GB/s per lane, one direction.

L2·Q2

PCIe 4.0 x8 link ki one-direction link bandwidth compute karo.

Recall Solution

Step A — raw rate: Gen 4 $= 16.0$ GT/s. Step B — efficiency apply karo (KYUN: 128b/130b encoding overhead remove karo taaki sirf payload bits bachein). Result Gbps mein hai, gigabits of payload per second: $16.0 \times \frac{128}{130} = 15.754 Gbps$ Step C — bits ko bytes mein convert karo (KYUN: 8 bits per byte, isliye GB/s paane ke liye 8 se divide karo): $\frac{15.754}{8} = 1.969 GB/s per lane$ Step D — lanes se scale karo (KYUN: 8 independent parallel channels har ek yeh rate simultaneously carry karte hain): $8 \times 1.969 = 15.75 GB/s$ Answer: $\approx 15.75$ GB/s one direction.

L2·Q3

PCIe 2.0 x16 link — one-direction bandwidth GB/s mein?

Recall Solution

Step A — raw rate: Gen 2 $= 5.0$ GT/s, encoding 8b/10b isliye efficiency $0.8$ . Step B — efficiency apply karo (KYUN: 20% 8b/10b overhead strip karo taaki payload bits bachein, Gbps milein): $5.0 \times 0.8 = 4.0 Gbps$ Step C — bits ko bytes mein convert karo (KYUN: 8 bits per byte, isliye GB/s tak pahunchne ke liye 8 se divide karo): $\frac{4.0}{8} = 0.5 GB/s per lane$ Step D — lanes se scale karo (KYUN: 16 parallel channels): $16 \times 0.5 = 8.0$ GB/s. Answer: $8.0$ GB/s one direction.

Level 3 — Analysis

Goal: compare karna, subtract karna, aur "maine kya khoya/paaya" ke baare mein reason karna.

L3·Q1

Ek NVMe drive (NVMe Protocol) PCIe 4.0 x4 pe 7000 MB/s sequential reads advertise karta hai. Kya yeh us link pe physically possible hai? Woh theoretical maximum ke kitne fraction pe link use kar raha hai?

Recall Solution

Step A — theoretical max, PCIe 4.0 x4: $4 \times 1.969 = 7.876 GB/s$ Step B — dono numbers ko same units mein rakho (KYUN: MB/s vs GB/s): $7000 MB/s = 7.0 GB/s$ Step C — compare karo: $7.0 < 7.876$ ✓ — physically possible. Step D — utilization: $\frac{7.0}{7.876} \times 100 \approx 88.9%$ Bacha hua ~11% NVMe command overhead, NAND read latency, aur controller limits mein kho jaata hai.

L3·Q2

Ek GPU jo PCIe 4.0 x16 pe run karne ke liye bana hai, accidentally PCIe 3.0 x4 ke liye wired slot mein lagaya jaata hai. Ek-direction bandwidth kitna GB/s mein lost hota hai, aur intended value ke percentage ke roop mein?

Recall Solution

Intended — Gen 4 x16: $16 \times 1.969 = 31.51$ GB/s. Actual — Gen 3 x4: ek saath do downgrades (generation aur width dono): $4 \times 0.985 = 3.94 GB/s$ Loss (GB/s): $31.51 - 3.94 = 27.57$ GB/s. Retained fraction: $\frac{3.94}{31.51} \times 100 \approx 12.5%$ — tumne sirf ek-aathvan rakha. Yeh itna brutal kyun hai: width $4 \times$ giri (x16→x4) aur per-lane rate ~ $2 \times$ giri (Gen4→Gen3). Dono multiply karo: $4 \times 2 = 8 \times$ slower. Dekho GPU Bandwidth Requirements.

L3·Q3

PCIe 3.0 x16 aur PCIe 4.0 x8 compare karo. Kaun sa zyada one-direction bandwidth deliver karta hai, aur kitna?

Recall Solution

Gen 3 x16: $16 \times 0.985 = 15.75$ GB/s. Gen 4 x8: $8 \times 1.969 = 15.75$ GB/s. Yeh equal hain (dono $\approx 15.75$ GB/s). KYUN: Gen 4, Gen 3 ke mukable per-lane rate double karta hai, isliye lane count ko aadha karne se exactly cancel ho jaata hai. Yeh general "one generation up = same throughput ke liye aadhe lanes" rule hai.

Level 4 — Synthesis

Goal: bifurcation, direction, aur multi-device reasoning combine karna.

L4·Q1

Ek PCIe 4.0 x16 slot bifurcation (PCIe Bifurcation) ko x8/x8 mein support karta hai. Do PCIe 4.0 x8 NVMe adapters install kiye jaate hain. Batao (a) har device ki one-direction bandwidth, (b) combined one-direction bandwidth, (c) kya koi bandwidth destroy hui.

Recall Solution

(a) Har device x8 dekhta hai: $8 \times 1.969 = 15.75$ GB/s. (b) Combined: $15.75 \times 2 = 31.5$ GB/s — original x16 total ke identical. (c) Kuch bhi destroy nahi hua — 16 lanes divide hue, khoye nahi. Lekin ab har individual device 15.75 GB/s pe capped hai, full 31.5 GB/s ki jagah. Bifurcation split karta hai, shrink nahi karta.

L4·Q2

Ek single PCIe 5.0 x16 link ke liye, one-direction aur bidirectional aggregate bandwidth dono do. Explain karo kyun aggregate woh number nahi hai jo tum RAM se textures read karte GPU ke liye quote karoge.

Recall Solution

Per lane, Gen 5 (32.0 GT/s): $\frac{32.0 \times \frac{128}{130}}{8} = \frac{31.508}{8} = 3.938 GB/s$ One direction, x16: $16 \times 3.938 = 63.02$ GB/s. Bidirectional aggregate (KYUN: har lane full-duplex hai — TX aur RX simultaneously run karte hain): $63.02 TX + 63.02 RX = 126.03 GB/s$ Texture reads ke liye one-direction kyun quote karein: GPU texture fetch ke dauran data ek taraf pull kar raha hai (RAM → GPU). Sirf RX direction woh kaam kar raha hai. Aggregate return path ko double-count karta hai jo tum use nahi kar rahe, isliye woh real throughput ko overstate karta hai. Dekho PCIe Electrical Signaling ki dono directions physically alag wire pairs hain.

Level 5 — Mastery

Goal: multi-step, real-hardware reasoning jahan ek galat assumption poora answer sink kar de.

L5·Q1

Ek workstation CPU total 16 PCIe 5.0 lanes expose karta hai. Chipset (CPU se ek separate link ke zariye connected) peripherals ke liye additionally 4 PCIe 4.0 lanes expose karta hai. Ek user chahta hai: ek GPU jise kam se kam 32 GB/s one-direction chahiye, aur ek NVMe drive jise kam se kam 7 GB/s one-direction chahiye. Ek concrete lane plan propose karo aur har device ke liye delivered bandwidth dikhao.

Recall Solution

Per-lane rates jo hum use karenge:

Gen 5 lane $= 3.938$ GB/s (L4·Q2 se).
Gen 4 lane $= 1.969$ GB/s (L2·Q2 se).

Step 1 — GPU ko kitne CPU lanes chahiye? Requirement $\geq 32$ GB/s. $\frac{32}{3.938} = 8.13 lanes$ PCIe widths powers of two tak quantized hain, isliye 8.13 agle valid width tak upar round hota hai — x16. Check karo: Gen 5 x8 deta hai $8 \times 3.938 = 31.5$ GB/s, jo strict target se neeche hai, isliye x8 fail karta hai. GPU ko poora x16 lena hoga. GPU delivered: $16 \times 3.938 = 63.02$ GB/s (comfortably $\geq 32$ ). Yeh saare 16 CPU lanes consume karta hai.

Step 2 — SSD kahan jaayega? 16 CPU lanes ab GPU ke liye fully committed hain, isliye SSD unhe use nahi kar sakta. Ise 4 chipset lanes (PCIe 4.0) route karo: $4 \times 1.969 = 7.88 GB/s$ SSD delivered: $7.88$ GB/s $\geq 7$ GB/s ✓.

Concrete plan:

GPU → CPU lanes, Gen 5 x16 → 63.02 GB/s ( $\geq 32$ meet karta hai).
SSD → chipset lanes, Gen 4 x4 → 7.88 GB/s ( $\geq 7$ meet karta hai).

Mastery insight: 16 Gen-5 CPU lanes ek x8 device ko zyada se zyada 31.5 GB/s dete hain, isliye strict " $\geq 32$ to GPU" GPU ko poora x16 claim karne par majboor karta hai. Isse SSD ke liye zero CPU lanes bachte hain, aur exactly isliye dusri device chipset lanes pe rehni chahiye (Motherboard Lane Allocation). Arithmetic — slot layout nahi — routing dictate karta hai.

L5·Q2

Parent note ki Master Table entry verify karo: PCIe 5.0 x16 = 63.02 GB/s one-direction. Phir dikhao ki ek Gen 3 x16 link ko bidirectional aggregate mein run karna hoga single-direction Gen 4 x16 se match karne ke liye — kya yeh possible hai?

Recall Solution

Gen 5 x16 one-direction verify karo: $16 \times \frac{32.0 \times \frac{128}{130}}{8} = 16 \times 3.938 = 63.02 GB/s ✓$ Gen 4 x16 one-direction: $16 \times 1.969 = 31.51$ GB/s. Gen 3 x16 one-direction: $16 \times 0.985 = 15.75$ GB/s. Gen 3 x16 aggregate (dono directions): $15.75 \times 2 = 31.5$ GB/s. Comparison: $31.5 \approx 31.51$ — Gen 3 x16 aggregate numerically Gen 4 x16 one-direction ke equal hai. Lekin yeh real match NAHI hai: aggregate TX+RX count karta hai; Gen 4 one-direction figure ek single stream mein achievable hai. Ek-taraf texture pull return path borrow nahi kar sakta. Isliye yeh equality arithmetic ka coincidence hai, usable throughput ka nahi. Mastery insight: hamesha like conventions compare karo — one-direction vs one-direction, aggregate vs aggregate. Unhe mix karne se "equal" numbers milte hain jo bilkul alag capabilities describe karte hain.

Recall Self-Test Checklist

One-line self-checks — reveal karne se pehle jawab do. Do encoding efficiencies aur unki generations kya hain? ::: 8b/10b = 0.8 Gen 1–2 ke liye; 128b/130b ≈ 0.9846 Gen 3+ ke liye. Master chain mein exactly kab 8 se divide karte hain? ::: Ek baar, efficiency apply karne ke baad, bits ko bytes mein convert karne ke liye — lane count se scale karne se pehle. Gen 4 x8, Gen 3 x16 se tie kyun karta hai? ::: Gen 4 per-lane rate double karta hai; lanes aadhe karne se cancel ho jaata hai → same 15.75 GB/s. Kya bifurcation total bandwidth reduce karta hai? ::: Nahi — yeh lanes divide karta hai; total unchanged rehta hai, lekin har device apne share pe capped hota hai. Ek-taraf GPU texture read ke liye kaun sa figure quote karein? ::: One-direction bandwidth, kabhi bhi bidirectional aggregate nahi.