PCIe lanes, links, and bandwidth: Worked examples — Hinglish deep dive

6.3.3 · D3 · Hardware › Interconnects, Buses & SoC › PCIe lanes, links, and bandwidth

Yeh page PCIe lanes, links, and bandwidth ka drill ground hai. Parent note ne raw signalling rate se full-duplex aggregate tak ka six-step bandwidth formula banaya tha. Yahan hum us machine ko lete hain aur usmein har tarah ka input daalte hain jo kabhi bhi aa sakta hai — bade lanes, chhote lanes, mismatched generations, number zero, ek bifurcated slot, ek word problem, aur ek exam trap — taaki koi bhi scenario tumhe kabhi surprise na kare.

Examples se pehle hum ek map of all the cases rakhte hain. Neeche har worked example us map-cell ke saath stamp kiya gaya hai jo use cover karta hai, taaki tum dekh sako ki kuch bhi chhoota nahi.

The one formula everything comes from

Is page par sab kuch ek hi chain hai. Pehle har piece ko plain words mein name karte hain, taaki koi bhi symbol bina explanation ke na aaye.

Yeh wala tool kyun aur, say, rates add karna kyun nahi? Kyunki charo effects independent multipliers hain, additions nahi. Lanes ko half karna aur efficiency ko half karna dono result ko same proportion se cut karte hain, isliye woh multiply karte hain. Addition se units mix ho jaate (GT/s + lanes meaningless hai).

The scenario matrix

Neeche woh har class of input hai jo yeh topic tumpar throw kar sakta hai. Har row ek alag "shape" of problem hai; last column us example ka naam batata hai jo ise pin karta hai.

Cell	Case class	Kya stress ho raha hai	Covered by
A	Plain forward calc (one gen, one width)	Core chain, no traps	Example 1
B	Byte↔bit / MB↔GB unit gymnastics	Marketers wale units ke beech convert karna	Example 2
C	Mismatched generation aur width (negotiated down)	Ek saath do cheezein galat	Example 3
D	Bifurcation split (one slot → two links)	Lanes divide karna, total conserve karna	Example 4
E	Full-duplex aggregate vs one-way	×2 trap	Example 5
F	Zero / degenerate input ( $N = 0$ , disconnected, x1)	Edge aur smallest cases	Example 6
G	Reverse solve (given BW, find lanes)	Chain ko ulta chalana	Example 7
H	Real-world word problem (bottleneck reasoning)	Kaunsa link limit hai?	Example 8
I	Exam-style twist (per-lane Gen numbers hidden)	Wording mein trap padhna	Example 9

Reference numbers jo hum baar baar use karte hain (sab one-direction, parent ke master table se):

Gen	$R$ (GT/s)	$η$	Per-lane GB/s
1.0	2.5	0.8	0.250
2.0	5.0	0.8	0.500
3.0	8.0	128/130	0.985
4.0	16.0	128/130	1.969
5.0	32.0	128/130	3.938

Worked examples

Worked example Example 1 — Cell A: plain forward calc

Statement. PCIe 3.0 x8 link ki one-way bandwidth kya hai?

Forecast: abhi andaaza lagao — kya yeh 8 GB/s se upar hai ya neeche? Likh lo.

Numbers pick karo: Gen 3.0 → $R = 8.0$ GT/s, $η = \frac{128}{130}$ . Yeh step kyun? Chain ko $R$ aur $η$ chahiye; dono generation se fix hote hain, width se nahi.
Per-lane data rate bits mein: $8.0 \times \frac{128}{130} = 7.877$ Gbps. Yeh step kyun? $R \times η$ encoding overhead strip kar deta hai, payload bits/s bachta hai.
Per-lane bytes mein: $7.877/8 = 0.985$ GB/s. Yeh step kyun? 8 se divide karo kyunki ek byte 8 bits ka hota hai — pure unit change.
Width se scale karo: $N = 8$ → $8 \times 0.985 = 7.877$ GB/s. Yeh step kyun? Lanes parallel aur independent hain, isliye bandwidth linearly scale hoti hai.

Answer: ≈ 7.88 GB/s (one way).

Verify: Units: $GT/s \times (unitless) \times lanes \times \frac{1}{8}$ = GB/s ✓. Sanity: x8 x16 ka half hai, aur Gen 3.0 x16 table mein 15.75 GB/s hai; uska half 7.88 hai ✓.

Worked example Example 2 — Cell B: unit gymnastics

Statement. Ek datasheet kehti hai "984 MB/s per lane, Gen 3.0." Kya yeh wahi lane rate hai jo humne compute ki?

Forecast: MB/s vs GB/s — kya numbers match karenge ya 1000 se off honge?

Hamari lane rate $0.985$ GB/s thi. MB/s mein convert karo. Yeh step kyun? Datasheet megabytes use karta hai; compare karne se pehle hum same unit use karein.
PCIe land mein $1 GB/s = 1000 MB/s$ (decimal, powers of ten — not 1024). Yeh step kyun? PCIe throughput SI decimal units mein quote hoti hai, isliye koi $2^{10}$ factor nahi aata.
$0.985 GB/s \times 1000 = 985 MB/s$ . Yeh step kyun? Prefix change karne ke liye seedha multiply karo.

Answer: Datasheet ka 984 vs hamare 985 — ek 1 MB/s rounding gap. Same number.

Verify: Round-trip: $985/1000 = 0.985$ GB/s, wapas wahi se jo humne shuru kiya ✓. Agar hum galti se 1024 use karte, toh $0.985 \times 1024 = 1008$ MB/s milta — clearly woh nahi jo sheet kehti hai, confirming decimal sahi hai.

Worked example Example 3 — Cell C: ek saath do cheezein galat

Statement. Ek GPU jo PCIe 4.0 x16 ke liye tha woh ek aise slot mein baitha jo PCIe 3.0 x4 negotiate karta hai. Kya one-way bandwidth bachti hai, aur intended ka kya fraction hai? (Dekho Motherboard Lane Allocation.)

Forecast: kya half se zyada gaya, ya kam? Commit karo.

Intended: Gen 4.0 x16 → $16 \times 1.969 = 31.51$ GB/s. Yeh step kyun? Yeh woh target hai jisse hum compare karte hain.
Actual: Gen 3.0 x4 → $4 \times 0.985 = 3.94$ GB/s. Yeh step kyun? Dono knobs change hue: lower $R, η$ (Gen 3 not 4) aur fewer lanes (4 not 16). Hume dono apply karne honge.
Fraction kept: $3.94/31.51 = 0.125 = 12.5%$ . Yeh step kyun? Ek ratio batata hai ki hum kitne throttle ho rahe hain, units se independent.

Answer: 3.94 GB/s, sirf 12.5% of intended.

Verify: Factors se sanity check: width $16 \to 4$ gayi = $\frac{1}{4}$ ; per-lane $1.969 \to 0.985$ gayi = $\frac{1}{2}$ . Product $\frac{1}{4} \times \frac{1}{2} = \frac{1}{8} = 12.5%$ ✓ — direct ratio se match karta hai.

Worked example Example 4 — Cell D: bifurcation split

Statement. Ek PCIe 4.0 x16 slot ko do NVMe cards ke liye bifurcated karke x8/x8 kiya gaya. Har card ko kya milta hai, aur total kya hai?

Forecast: kya har card ko poora x16 rate milta hai, half milta hai, ya kuch aur?

Har link ab Gen 4.0 x8 hai: $8 \times 1.969 = 15.75$ GB/s. Yeh step kyun? Bifurcation har device ko uska apna independent x8 link deta hai — har ek x8 dekhta hai, x16 kabhi nahi.
Dono mein total: $15.75 \times 2 = 31.51$ GB/s. Yeh step kyun? Dono links ek hi 16 physical lanes par simultaneously chalte hain, isliye aggregate original x16 ke barabar hai.

Answer: 15.75 GB/s each, 31.51 GB/s total.

Verify: Conservation check — split lanes total conserve karni chahiye: original x16 = $16 \times 1.969 = 31.51$ GB/s, aur $2 \times 15.75 = 31.51$ ✓. Koi bandwidth create ya destroy nahi hui; woh divide hui.

Worked example Example 5 — Cell E: full-duplex ×2 trap

Statement. Ek spec sheet chillati hai "PCIe 5.0 x16 = 128 GB/s!" Tumhara one-way calc ~63 GB/s deta hai. Kaun sahi hai?

Forecast: kya sheet jhooth bol rahi hai, ya kuch aisa count kar rahi hai jo tum nahi kar rahe?

One-way: $16 \times 3.938 = 63.02$ GB/s. Yeh step kyun? Yeh payload hai ek direction mein (e.g. host→GPU).
Aggregate: har lane full-duplex hai, isliye TX aur RX ek saath hote hain: $63.02 \times 2 = 126.03$ GB/s. Yeh step kyun? Bidirectional aggregate dono directions add karta hai — woh ×2 jo marketing use karta hai.

Answer: Dono "sahi" hain par alag sawaalon ke jawaab dete hain: 63 GB/s one-way, ~126 GB/s aggregate (ads mein "128" rounded).

Verify: Marketing ka "128" raw $32 GT/s \times 16 \times 2/8 = 128$ GB/s encoding ignore karke aata hai. Encoding ke saath yeh 126.03 hai — isliye honest aggregate $126.03$ hai, aur raw-bits-ignored figure $128$ hai. Dono traceable hain ✓.

Worked example Example 6 — Cell F: zero aur degenerate inputs

Statement. Teen edge cases: (a) ek disconnected card x0 negotiate karta hai; (b) smallest real link, Gen 1.0 x1; (c) formula ka kya hota hai jab $N \to 0$ .

Forecast: kya formula zero par break karta hai, ya gracefully zero deta hai?

(a) $N = 0$ : $0 \times (anything) = 0$ GB/s. Yeh step kyun? Zero se multiplication — koi lanes nahi matlab koi channels nahi matlab koi data nahi. Formula degenerate point par bhi valid rehta hai.
(b) Gen 1.0 x1: $1 \times 0.250 = 0.250$ GB/s. Yeh step kyun? Smallest generation, smallest width — poore table ka floor.
(c) Limit: kyunki bandwidth $= N \times (const)$ hai, yeh $N$ mein linear hai, isliye $N \to 0$ par yeh smoothly 0 ki taraf jaata hai slope = per-lane rate ke saath. Yeh step kyun? Linearity ka matlab koi surprises nahi, koi discontinuity nahi — "zero lanes wali highway" exactly zero traffic carry karti hai.

Answer: x0 → 0 GB/s; Gen 1.0 x1 → 0.250 GB/s; map continuous hai aur origin se guzarti hai.

Verify: $N = 1$ Gen 1.0 mein plug karo: $2.5 \times 0.8/8 = 0.25$ ✓. $N = 0$ plug karo: exactly $0$ ✓. Inke beech slope = $0.25$ GB/s per lane, per-lane rate se match karta hai ✓.

Yeh rahi woh linearity drawn — bandwidth origin se ek seedhi ray hai, ek line per generation:

Figure — PCIe lanes, links, and bandwidth

Worked example Example 7 — Cell G: chain ko ulta chalao

Statement. Ek device PCIe 4.0 link par 7.0 GB/s one-way sustain karta hai. Minimum lane width kya hogi joh usne negotiate ki hogi?

Forecast: x2, x4, ya x8?

Per-lane Gen 4.0 rate = 1.969 GB/s. Yeh step kyun? Lanes find karne ke liye hum $BW = N \times (per-lane)$ invert karte hain, isliye per-lane value chahiye.
$N$ ke liye solve karo: $N = \frac{7.0}{1.969} = 3.55$ . Yeh step kyun? Observed BW ko per-lane rate se divide karne par fractional lanes needed milti hain.
Legal width tak upar round karo: $3.55 \to$ next valid hai x4. Yeh step kyun? Lanes sirf 1, 2, 4, 8, 16 mein aate hain. 3.55 lanes nahi khareed sakte; x2 (= $3.94$ GB/s cap... wait, $2 \times 1.969 = 3.94 < 7.0$ ) chota hai, isliye x4 minimum hai jo fit hota hai.

Answer: x4 (jo $4 \times 1.969 = 7.877$ GB/s tak cap karta hai, 7.0 se comfortably upar).

Verify: Check x2 fails: $2 \times 1.969 = 3.94 < 7.0$ ✗. Check x4 works: $7.877 \geq 7.0$ ✓. Isliye x4 minimum hai.

Worked example Example 8 — Cell H: real-world bottleneck

Statement. Ek NVMe SSD 7000 MB/s rated hai aur PCIe 4.0 x4 par chalta hai, lekin tum ise ek chipset uplink se route karte ho jo doosre devices ke saath shared hai, effectively use PCIe 3.0 x4 kar deta hai. Kya woh abhi bhi 7000 MB/s hit kar sakta hai? Ceiling kya hai?

Forecast: kya drive apni rating rakhe hogi, ya uplink ise strangle karega?

Drive rating GB/s mein: $7000/1000 = 7.0$ GB/s. Yeh step kyun? Units ko link se match karo (GB/s) compare karne se pehle — Cell B ka lesson.
Effective link ceiling: Gen 3.0 x4 = $4 \times 0.985 = 3.94$ GB/s. Yeh step kyun? Path ka sabse slow link ceiling set karta hai — yahi bottleneck rule hai.
Compare: $7.0 > 3.94$ , isliye link, drive nahi, limit hai. Yeh step kyun? Ek chain ki bandwidth = uska sabse narrow link, exactly jaise paani sabse patli pipe se guzarta hai.

Answer: Nahi — 3.94 GB/s par capped, drive ki rating ka roughly 56% ( $3.94/7.0$ ).

Verify: Correct Gen 4.0 x4 link par ceiling $4 \times 1.969 = 7.877 \geq 7.0$ hai ✓ (drive fit ho jaata), confirming loss purely generation downgrade ki wajah se hai. Ratio $3.94/7.877 = 0.5$ ✓ — Gen 3 per lane exactly Gen 4 ka half hai.

Worked example Example 9 — Cell I: exam twist

Statement. Exam question: "Ek PCIe 2.0 x16 link aur ek PCIe 3.0 x8 link — kaun zyada one-way bandwidth deliver karta hai?" Trap: zyada lanes ≠ zyada bandwidth.

Forecast: x16 (zyada lanes) ya x8 (newer gen)?

PCIe 2.0 x16: per-lane $= 5.0 \times 0.8/8 = 0.5$ GB/s, isliye $16 \times 0.5 = 8.0$ GB/s. Yeh step kyun? Old gen ka $η = 0.8$ aur low $R$ hai, lekin bahut lanes hain.
PCIe 3.0 x8: per-lane $= 0.985$ GB/s, isliye $8 \times 0.985 = 7.877$ GB/s. Yeh step kyun? Newer gen, richer $η$ , lekin half lanes.
Compare: $8.0 > 7.877$ . Yeh step kyun? Direct numbers settle karte hain; intuition ("newer is faster") yahan mislead karti.

Answer: PCIe 2.0 x16 jeet jaata hai, barely — 8.0 vs 7.88 GB/s.

Verify: Difference $8.0 - 7.877 = 0.123$ GB/s ≈ 1.6% — ek photo-finish jo unhe punish karta hai jo gut se guess karte hain ✓.

Recall Quick self-test

Gen 3.0 x8 one-way bandwidth? ::: ≈ 7.88 GB/s A card reads "x16 @ x8" — how many real lanes? ::: 8 (doosra number negotiated width hai) Why do bandwidth contributions multiply, not add? ::: $R$ , $η$ , aur $N$ independent proportional factors hain; add karne se incompatible units mix ho jaate An x16 slot bifurcated x8/x8 — bandwidth per device? ::: har ek ko x16 link ka half; total conserved Marketing "128 GB/s" for Gen5 x16 vs your 63 GB/s — the gap? ::: woh bidirectional aggregate (×2) quote karte hain aur aksar encoding ignore karte hain

Where to go next

Encoding fractions 8b10b Encoding aur 128b130b Encoding se aaye hain.
Lanes physically pairs mein kyun exist karte hain: PCIe Electrical Signaling.
CPU/chipset kaise decide karta hai ki kaunse slot ko kitne lanes milenge: Motherboard Lane Allocation aur PCIe Bifurcation.
Kya ek card actually full width use bhi karta hai: GPU Bandwidth Requirements.
Bada picture: PCIe Architecture Overview aur parent PCIe lanes, links, and bandwidth.